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path: root/src/vhdl/vhdl-ieee-std_logic_1164.adb
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* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-111-0/+27
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-4/+16
* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-051-0/+7
* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-011-0/+4
* update license headersumarcor2021-01-141-11/+9
* vhdl: recognize logica vec/log and log/vec operators. For #1520Tristan Gingold2020-12-031-0/+82
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-0/+1
* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-0/+7
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-4/+10
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-0/+2
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-0/+43
* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-0/+44
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-0/+6
* vhdl-ieee-std_logic_1164: minor simplification.Tristan Gingold2019-11-061-21/+8
* synth: handle edge operators in synth_predefined_function_call.Tristan Gingold2019-11-061-3/+4
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-061-6/+12
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-071-81/+72
* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-301-5/+15
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-201-5/+18
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-1/+1
* vhdl: move ieee packages to vhdl children.Tristan Gingold2019-05-051-0/+319