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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
| commit | 67f926fc1323c375d14fee36a092e39a92d505dd (patch) | |
| tree | 2721ed6d11218bd9db3358e913d08f874dc9bc6a /src/vhdl/vhdl-ieee-std_logic_1164.adb | |
| parent | defe3b033f1c3026312c94e5ce661172c670e9a5 (diff) | |
| download | ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.gz ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.bz2 ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.zip | |
synth: handle reduction operators. Fix #1342
Diffstat (limited to 'src/vhdl/vhdl-ieee-std_logic_1164.adb')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 58fe96229..bb4b12bce 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -375,11 +375,17 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Not => Predefined := Iir_Predefined_Ieee_1164_Vector_Not; when Name_And => - Predefined := - Iir_Predefined_Ieee_1164_Vector_And_Reduce; + Predefined := Iir_Predefined_Ieee_1164_And_Suv; + when Name_Nand => + Predefined := Iir_Predefined_Ieee_1164_Nand_Suv; when Name_Or => - Predefined := - Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + Predefined := Iir_Predefined_Ieee_1164_Or_Suv; + when Name_Nor => + Predefined := Iir_Predefined_Ieee_1164_Nor_Suv; + when Name_Xor => + Predefined := Iir_Predefined_Ieee_1164_Xor_Suv; + when Name_Xnor => + Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => Predefined := Iir_Predefined_Ieee_1164_Scalar_Is_X; |