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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-06 19:09:28 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-06 19:09:28 +0100 |
| commit | e89e64a25bc2bceb40c3beca78a842df9c257dfa (patch) | |
| tree | 304c8121368bcdea778e41493ef3773db092bd38 /src/vhdl/vhdl-ieee-std_logic_1164.adb | |
| parent | c6023180ffa061cf4394633642763b7d3546c737 (diff) | |
| download | ghdl-e89e64a25bc2bceb40c3beca78a842df9c257dfa.tar.gz ghdl-e89e64a25bc2bceb40c3beca78a842df9c257dfa.tar.bz2 ghdl-e89e64a25bc2bceb40c3beca78a842df9c257dfa.zip | |
synth: handle edge operators in synth_predefined_function_call.
Diffstat (limited to 'src/vhdl/vhdl-ieee-std_logic_1164.adb')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index d88a45ccb..50beaa554 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -120,6 +120,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is is Error : exception; + Rising_Edge : Iir_Function_Declaration := Null_Iir; + Falling_Edge : Iir_Function_Declaration := Null_Iir; + Decl : Iir; Def : Iir; Predefined : Iir_Predefined_Functions; @@ -234,7 +237,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is case Get_Identifier (Decl) is when Name_Rising_Edge => Rising_Edge := Decl; - Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; + Predefined := Iir_Predefined_Ieee_1164_Rising_Edge; when Name_Falling_Edge => Falling_Edge := Decl; Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; @@ -333,7 +336,5 @@ package body Vhdl.Ieee.Std_Logic_1164 is Std_Logic_Vector_Type := Null_Iir; Std_Ulogic_0 := Null_Iir; Std_Ulogic_1 := Null_Iir; - Rising_Edge := Null_Iir; - Falling_Edge := Null_Iir; end Extract_Declarations; end Vhdl.Ieee.Std_Logic_1164; |