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* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-091-2/+7
* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-1/+1
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-0/+6
* vhdl-annotations: annotate procedure call associationsTristan Gingold2022-05-251-14/+47
* vhdl-annotations: do not annotate type for signal attributesTristan Gingold2022-04-291-2/+0
* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-131-1/+3
* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-1/+2
* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-051-31/+21
* synth: fix handling of record constraints in subtype. Fix #1961Tristan Gingold2022-02-221-4/+19
* synth: do not annotate generic types in package. Fix #1949Tristan Gingold2022-01-151-1/+4
* vhdl: add commentsTristan Gingold2022-01-151-1/+6
* synth: handle macro-expanded package body. Fix #1948Tristan Gingold2022-01-141-4/+12
* synth: refine handling of interface type. Fix #1944Tristan Gingold2022-01-101-6/+16
* synth: handle interface type in generics. For #412Tristan Gingold2021-12-151-3/+8
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+23
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-051-10/+11
* synth: Support alias declarations in vunittmeissner2021-11-021-1/+3
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-28/+42
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-1/+2
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+1
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-4/+0
* update license headersumarcor2021-01-141-11/+9
* vhdl-sem_decls: handle multiple declarations with subtype attribute.Tristan Gingold2020-07-181-2/+6
* vhdl-annotations: adjust after change of subtype_indication.Tristan Gingold2020-07-011-1/+1
* vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641Tristan Gingold2020-06-301-1/+1
* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-1/+6
* synth-decls: handle unbounded record subtypes. Fix #1324Tristan Gingold2020-05-191-12/+13
* vhdl-utils: factorize Get_File_Signature.Tristan Gingold2020-05-151-66/+0
* synth: fix handling of subtype indication in object aliases for vhdl 2008.Tristan Gingold2020-03-291-1/+4
* synth: avoid crash on bad elaboration order.Tristan Gingold2020-03-091-1/+3
* synth: handle deferred constants. Fix #1096Tristan Gingold2020-01-161-0/+3
* synth: support multiple synthesis.Tristan Gingold2019-12-021-0/+28
* synth: file support (WIP).Tristan Gingold2019-11-121-1/+2
* synth: initial support for file types. For #1004Tristan Gingold2019-11-111-27/+33
* synth: initial support of access type. For #1004Tristan Gingold2019-11-111-0/+4
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-1/+3
* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-251-0/+2
* vhdl-annotations: extract annotate_concurrent_statement.Tristan Gingold2019-10-251-47/+53
* vhdl-annotations: minor renaming.Tristan Gingold2019-10-251-8/+8
* vhdl-annotations: handle some declarations in vunits.Tristan Gingold2019-10-231-0/+6
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-1/+3
* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-071-1/+2
* synth: handle record subtypes.Tristan Gingold2019-09-191-5/+8
* vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
* vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
* synth: add support for record types.Tristan Gingold2019-08-291-0/+4
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-271-0/+1
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-1/+2
* synth: handle verification units.Tristan Gingold2019-08-201-1/+29
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