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| author | Tristan Gingold <tgingold@free.fr> | 2021-10-13 20:21:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-10-13 20:21:22 +0200 |
| commit | ff3105a7a8b8298771c64fd13171e33385f6fcc8 (patch) | |
| tree | bb62de013a34b3742ce06377a75593ba45a13338 /src/vhdl/vhdl-annotations.adb | |
| parent | 3486a9d34f6cdb83e5917da9b20a6e5bf9f13b81 (diff) | |
| download | ghdl-ff3105a7a8b8298771c64fd13171e33385f6fcc8.tar.gz ghdl-ff3105a7a8b8298771c64fd13171e33385f6fcc8.tar.bz2 ghdl-ff3105a7a8b8298771c64fd13171e33385f6fcc8.zip | |
synth: add support for sequence instance in vunit. Fix #1889
Diffstat (limited to 'src/vhdl/vhdl-annotations.adb')
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 36a61238e..fae87203a 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1138,7 +1138,8 @@ package body Vhdl.Annotations is Item := Get_Vunit_Item_Chain (Decl); while Item /= Null_Iir loop case Get_Kind (Item) is - when Iir_Kind_Psl_Default_Clock => + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive |