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path: root/src/vhdl/simulate/simul-annotations.adb
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* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-291-1315/+0
* synth: get rid of execution and elaboration.Tristan Gingold2019-06-191-40/+53
* vhdl: decouple annotations from environments.Tristan Gingold2019-06-191-43/+24
* vhdl/simulate: fix regression wrt package instances.Tristan Gingold2019-06-121-1/+1
* simul: refine scalar type annotations.Tristan Gingold2019-06-121-13/+40
* synth: handle integer +/- for constants.Tristan Gingold2019-06-081-1/+2
* vhdl/simulate: ignore some constructs for synthesis.Tristan Gingold2019-05-231-2/+3
* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-191-10/+5
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-1/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* vhdl: move std_standard package to vhdl child.Tristan Gingold2019-05-051-4/+4
* simul: Add ref in info to ease debugging.Tristan Gingold2017-12-211-0/+23
* simul: add Kind_Protected instead of reusing Kind_Frame.Tristan Gingold2017-12-211-1/+7
* simul: handle psl endpoints (and adjust issue45).Tristan Gingold2017-12-211-0/+2
* simul: handle selected signal assignments.Tristan Gingold2017-12-211-0/+1
* simul: create initial driver value.Tristan Gingold2017-12-211-2/+2
* simul: fix crash while calling foreign subprogram.Tristan Gingold2017-12-111-2/+2
* simul: fix annotation of macro-expanded package instantiation.Tristan Gingold2017-12-071-5/+16
* simul: handle interface type.Tristan Gingold2017-12-071-1/+2
* simul: handle nested package instantiation.Tristan Gingold2017-12-071-1/+3
* simul: fix choice list for case generate statement.Tristan Gingold2017-12-051-2/+4
* simul: psl default clock, unaffected waveform.Tristan Gingold2017-12-051-0/+3
* simul: handle interface subprogram.Tristan Gingold2017-12-051-1/+4
* simul: handle package interface, remove iir_value_environment.Tristan Gingold2017-12-051-8/+8
* simul: handle instantiated package.Tristan Gingold2017-12-051-4/+11
* simul: add support for case generate statetement.Tristan Gingold2017-12-041-0/+15
* simul: support nested packages.Tristan Gingold2017-12-041-54/+59
* simul: Remove scope_type (unused).Tristan Gingold2017-12-031-152/+14
* simul: add global_info.Tristan Gingold2017-12-031-32/+45
* simul: refactoring: scope is now the corresponding sim_info.Tristan Gingold2017-12-031-22/+18
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-0/+1345