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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-19 18:12:20 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-21 07:36:47 +0100 |
| commit | 8bb2635ccecde036d92b242b2d43efd4372793a8 (patch) | |
| tree | 75475205b06180b935d89d34d97034802a7ae9cf /src/vhdl/simulate/simul-annotations.adb | |
| parent | 787ef6f900f18ea853c01edaf00f0e6836b61834 (diff) | |
| download | ghdl-8bb2635ccecde036d92b242b2d43efd4372793a8.tar.gz ghdl-8bb2635ccecde036d92b242b2d43efd4372793a8.tar.bz2 ghdl-8bb2635ccecde036d92b242b2d43efd4372793a8.zip | |
simul: handle selected signal assignments.
Diffstat (limited to 'src/vhdl/simulate/simul-annotations.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 9db4aad02..ba1d8c7ed 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -783,6 +783,7 @@ package body Simul.Annotations is when Iir_Kind_Return_Statement => null; when Iir_Kind_Simple_Signal_Assignment_Statement + | Iir_Kind_Selected_Waveform_Assignment_Statement | Iir_Kind_Variable_Assignment_Statement => null; when Iir_Kind_Procedure_Call_Statement => |