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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-05 05:19:27 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-05 05:19:27 +0100 |
| commit | 344ca60dd3b9cc8547951a5573b1bb209b3e7b5b (patch) | |
| tree | f06e09e77138bbc5f900de9c26583594ddf0f821 /src/vhdl/simulate/simul-annotations.adb | |
| parent | 237ff6b3749f8e8bcab5040fcb04feeec77da92b (diff) | |
| download | ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.tar.gz ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.tar.bz2 ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.zip | |
simul: psl default clock, unaffected waveform.
Diffstat (limited to 'src/vhdl/simulate/simul-annotations.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index fb03495e4..4c6e6e80b 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -717,6 +717,9 @@ package body Simul.Annotations is when Iir_Kind_Nature_Declaration => null; + when Iir_Kind_Psl_Default_Clock => + null; + when others => Error_Kind ("annotate_declaration", Decl); end case; |