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authorTristan Gingold <tgingold@free.fr>2019-05-05 07:49:25 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-05 08:05:11 +0200
commit85d360929d13e6b0bcb082f144883a43f402ce22 (patch)
treef8d8135e12393588b7704318f26304dfab272658 /src/vhdl/simulate/simul-annotations.adb
parent3c48cc2a70085eef63718e622b3d1a7b75a2f36f (diff)
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vhdl: move std_standard package to vhdl child.
Diffstat (limited to 'src/vhdl/simulate/simul-annotations.adb')
-rw-r--r--src/vhdl/simulate/simul-annotations.adb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index f02f642b1..22ca12a07 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -18,7 +18,7 @@
with Tables;
with Ada.Text_IO;
-with Std_Package;
+with Vhdl.Std_Package;
with Errorout; use Errorout;
with Iirs_Utils; use Iirs_Utils;
with Types; use Types;
@@ -279,8 +279,8 @@ package body Simul.Annotations is
declare
Mode : Iir_Value_Kind;
begin
- if Def = Std_Package.Boolean_Type_Definition
- or else Def = Std_Package.Bit_Type_Definition
+ if Def = Vhdl.Std_Package.Boolean_Type_Definition
+ or else Def = Vhdl.Std_Package.Bit_Type_Definition
then
Mode := Iir_Value_B1;
elsif (Get_Nbr_Elements (Get_Enumeration_Literal_List (Def))
@@ -1161,7 +1161,7 @@ package body Simul.Annotations is
Annotate_Architecture (El);
when Iir_Kind_Package_Declaration =>
declare
- use Std_Package;
+ use Vhdl.Std_Package;
begin
if El = Standard_Package then
pragma Assert (Global_Info = null);