iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: rework range.	Tristan Gingold	2019-07-26	5	-48/+52
*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	8	-42/+68
*	synth: handle array aggregate.	Tristan Gingold	2019-07-26	2	-27/+32
*	synth: handle bit.	Tristan Gingold	2019-07-25	3	-4/+11
*	synth: array inequality, integer in choices.	Tristan Gingold	2019-07-25	2	-0/+11
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	1	-0/+3
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	8	-66/+247
*	synth: fix incorrect slice in disp_vhdl for Insert.	Tristan Gingold	2019-07-25	1	-6/+1
*	synth: fix bad ordering in case statement.	Tristan Gingold	2019-07-24	1	-2/+3
*	synth: do not consider (unrecognized) ieee functions as user functions.	Tristan Gingold	2019-07-24	1	-0/+19
*	synth: handle resize.	Tristan Gingold	2019-07-24	1	-0/+15
*	synth: handle record type declarations.	Tristan Gingold	2019-07-24	1	-1/+11
*	synth: fix slice/indexed assignment that partially override previous assign.	Tristan Gingold	2019-07-23	1	-5/+8
*	synth: add more operators.	Tristan Gingold	2019-07-23	1	-1/+34
*	synth: fix to_unsigned.	Tristan Gingold	2019-07-23	1	-2/+2
*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	6	-20/+304
*	synth: remove bounds (unused) for ports.	Tristan Gingold	2019-07-22	4	-13/+4
*	synth: minor refactoring in netlists.disp_vhdl	Tristan Gingold	2019-07-22	2	-47/+54
*	synth: rework names.	Tristan Gingold	2019-07-22	6	-24/+25
*	add port width utility function for yosys (#876)	Pepijn de Vos	2019-07-21	4	-0/+18
*	synth: improve output (id_extract).	Tristan Gingold	2019-07-20	1	-6/+12
*	synth: improve output (for id_insert).	Tristan Gingold	2019-07-20	1	-11/+18
*	synth: add support for concurrent selected signal assignment.	Tristan Gingold	2019-07-20	1	-2/+138
*	synth: support index of a constant.	Tristan Gingold	2019-07-20	1	-0/+4
*	synth: initial support for for-generate statement.	Tristan Gingold	2019-07-20	2	-29/+89
*	synth: add and merge phi within a function.	Tristan Gingold	2019-07-20	1	-0/+5
*	synth: fix aggregate vectorize direction.	Tristan Gingold	2019-07-20	2	-5/+6
*	synth: add concatn gate	Tristan Gingold	2019-07-19	9	-32/+126
*	synth: finalize concurrent assignments (WIP).	Tristan Gingold	2019-07-19	6	-33/+342
*	synth: add const_z gate.	Tristan Gingold	2019-07-19	4	-3/+33
*	synth: make more types private.	Tristan Gingold	2019-07-17	2	-35/+48
*	synth: make type Wire_Id_Record private.	Tristan Gingold	2019-07-17	7	-44/+74
*	synth: renaming of Assign to Seq_Assign.	Tristan Gingold	2019-07-17	6	-79/+82
*	synth: add comments.	Tristan Gingold	2019-07-17	2	-0/+2
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	4	-25/+50
*	synth: handle instantiation within generate statement.	Tristan Gingold	2019-07-15	1	-0/+2
*	synth: handle choices by range in aggregates.	Tristan Gingold	2019-07-15	3	-12/+33
*	synth: handle anonymous subtypes in array subtypes.	Tristan Gingold	2019-07-15	1	-4/+10
*	synth: add comments.	Tristan Gingold	2019-07-15	1	-6/+10
*	synth: remove extra elaboration of port types.	Tristan Gingold	2019-07-15	1	-18/+2
*	synth: apply block configuration to for-generate statements.	Tristan Gingold	2019-07-15	1	-2/+15
*	synth: use correct instance to synth default expressions of assocs.	Tristan Gingold	2019-07-15	1	-10/+13
*	synth: save and restore instance_pool for processes.	Tristan Gingold	2019-07-15	1	-2/+4
*	synth: improve support of components (anon subtypes).	Tristan Gingold	2019-07-14	1	-0/+15
*	synth: handle anonymous signals.	Tristan Gingold	2019-07-14	1	-0/+3
*	synth: handle black boxes.	Tristan Gingold	2019-07-13	3	-47/+108
*	synth: handle simple component instances.	Tristan Gingold	2019-07-13	1	-36/+256
*	synth_top_entity: pass config + minor cleanup.	Tristan Gingold	2019-07-11	3	-13/+7
*	synth-insts: minor cleanup.	Tristan Gingold	2019-07-11	1	-7/+0
*	synth: do not crash on use of std_logic_1164 2008.	Tristan Gingold	2019-07-10	1	-2/+6