synth: handle bit.

3 files changed, 11 insertions, 4 deletions

diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 382726db4..c638c5616 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -97,7 +97,7 @@ package body Synth.Context is
                  Get_Info (Get_Base_Type (Obj_Type));
                Rng : Value_Bound_Acc;
             begin
-               if Info.Kind = Kind_Bit_Type then
+               if Is_Bit_Type (Obj_Type) then
                   Rng := null;
                else
                   Rng := Create_Value_Bound
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index c8049f570..d7a0699d9 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -196,6 +196,7 @@ package body Synth.Decls is
                Atype := Get_Named_Entity (Atype);
             when Iir_Kind_Subtype_Declaration
               | Iir_Kind_Type_Declaration =>
+               --  Type already declared, so already handled.
                return Null_Node;
             when Iir_Kind_Array_Subtype_Definition
               | Iir_Kind_Integer_Subtype_Definition
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 7c178b4f4..6aa0e78ad 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -420,14 +420,19 @@ package body Synth.Insts is
    procedure Create_Component_Wire (Inter : Node; Val : Value_Acc)
    is
       Value : Net;
+      W : Width;
    begin
       case Val.Kind is
          when Value_Wire =>
             --  Create a gate for the output, so that it could be read.
             Val.W := Alloc_Wire (Wire_Output, Inter);
+            if Val.W_Bound = null then
+               W := 1;
+            else
+               W := Val.W_Bound.Len;
+            end if;
             Value := Builders.Build_Signal
-              (Build_Context, New_Sname (No_Sname, Get_Identifier (Inter)),
-               Val.W_Bound.Len);
+              (Build_Context, New_Sname (No_Sname, Get_Identifier (Inter)), W);
             Set_Wire_Gate (Val.W, Value);
          when others =>
             raise Internal_Error;
@@ -676,7 +681,8 @@ package body Synth.Insts is
             --  Create a gate for the output, so that it could be read.
             Val.W := Alloc_Wire (Wire_Output, Inter);
             W := Get_Output_Desc (Get_Module (Self_Inst), Idx).W;
-            pragma Assert (W = Val.W_Bound.Len);
+            pragma Assert ((W = 1 and then Val.W_Bound = null)
+                           or else (W /= 1 and then W = Val.W_Bound.Len));
             Value := Builders.Build_Output (Build_Context, W);
             Set_Location (Value, Inter);
             Inp := Get_Input (Self_Inst, Idx);