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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-20 21:08:28 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-20 21:08:28 +0200 |
| commit | 56c7e71ecc72b528b4d246703b3ec406c7432e8a (patch) | |
| tree | ef82ada10cc5d0b0959264a3eded4f932c74c933 /src/synth | |
| parent | 7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f (diff) | |
| download | ghdl-56c7e71ecc72b528b4d246703b3ec406c7432e8a.tar.gz ghdl-56c7e71ecc72b528b4d246703b3ec406c7432e8a.tar.bz2 ghdl-56c7e71ecc72b528b4d246703b3ec406c7432e8a.zip | |
synth: improve output (for id_insert).
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 2bd1b9911..c05e1ade2 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -297,7 +297,7 @@ package body Netlists.Disp_Vhdl is if First then First := False; else - Put_Line (", "); + Put_Line (","); end if; Put (" "); Put_Interface_Name (Get_Output_Desc (Imod, Idx).Name); @@ -522,22 +522,29 @@ package body Netlists.Disp_Vhdl is when Id_Insert => declare Iw : constant Width := Get_Width (Get_Input_Net (Inst, 1)); + Ow : constant Width := Get_Width (Get_Output (Inst, 0)); Off : constant Uns32 := Get_Param_Uns32 (Inst, 0); begin - Disp_Template - (" process (\i0, \i1)" & NL & - " begin" & NL & - " \o0 <= \i0;" & NL, - Inst); + Disp_Template (" \o0 <= ", Inst); + if Off + Iw + 1 = Ow then + Disp_Template ("\i0 (\n0) & ", Inst, (0 => Ow - 1)); + elsif Off + Iw < Ow then + Disp_Template ("\i0 (\n0 downto \n1) & ", Inst, + (0 => Ow - 1, 1 => Off + Iw)); + end if; if Iw > 1 then - Disp_Template (" \o0 (\n0 downto \n1)", Inst, + Disp_Template ("\i1 (\n0 downto \n1)", Inst, (0 => Off + Iw - 1, 1 => Off)); else - Disp_Template (" \o0 (\n0)", Inst, (0 => Off)); + Disp_Template ("\i1", Inst); end if; - Disp_Template - (" <= \i1;" & NL & - " end process;" & NL, Inst); + if Off > 1 then + Disp_Template (" & \i0 (\n0 downto 0)", Inst, + (0 => Off - 1)); + elsif Off = 1 then + Disp_Template (" & \i0 (0)", Inst); + end if; + Disp_Template (";" & NL, Inst); end; when Id_Dyn_Insert => declare |