synth: renaming of Assign to Seq_Assign.

6 files changed, 82 insertions, 79 deletions

diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 0f32e2d7c..46c293c01 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -75,7 +75,7 @@ package body Synth.Context is
                              Mark_Flag => False,
                              Decl => Obj,
                              Gate => No_Net,
-                             Cur_Assign => No_Assign));
+                             Cur_Assign => No_Seq_Assign));
       return Wire_Id_Table.Last;
    end Alloc_Wire;
 
diff --git a/src/synth/synth-environment-debug.adb b/src/synth/synth-environment-debug.adb
index b1ac137c5..693d20068 100644
--- a/src/synth/synth-environment-debug.adb
+++ b/src/synth/synth-environment-debug.adb
@@ -32,10 +32,10 @@ package body Synth.Environment.Debug is
       Put (" Init: ");
       Dump_Net_Name (W_Rec.Gate);
       New_Line;
-      Put_Line (" cur_assign:" & Assign'Image (W_Rec.Cur_Assign));
+      Put_Line (" cur_assign:" & Seq_Assign'Image (W_Rec.Cur_Assign));
    end Dump_Wire_Id;
 
-   procedure Dump_Assign (Asgn : Assign)
+   procedure Dump_Assign (Asgn : Seq_Assign)
    is
       procedure Dump_Value (N : Net) is
       begin
@@ -47,13 +47,13 @@ package body Synth.Environment.Debug is
             Put ("unassigned");
          end if;
       end Dump_Value;
-      Rec : Assign_Record renames Assign_Table.Table (Asgn);
+      Rec : Seq_Assign_Record renames Assign_Table.Table (Asgn);
    begin
-      Put ("Assign" & Assign'Image (Asgn));
+      Put ("Assign" & Seq_Assign'Image (Asgn));
       Put (" Id:" & Wire_Id'Image (Rec.Id));
-      Put (", prev_assign:" & Assign'Image (Rec.Prev));
+      Put (", prev_assign:" & Seq_Assign'Image (Rec.Prev));
       Put (", phi:" & Phi_Id'Image (Rec.Phi));
-      Put (", chain:" & Assign'Image (Rec.Chain));
+      Put (", chain:" & Seq_Assign'Image (Rec.Chain));
       New_Line;
       Put (" value: ");
       Dump_Value (Rec.Value);
@@ -63,12 +63,12 @@ package body Synth.Environment.Debug is
    procedure Dump_Phi (Id : Phi_Id)
    is
       Phi : Phi_Type renames Phis_Table.Table (Id);
-      Asgn : Assign;
+      Asgn : Seq_Assign;
    begin
       Put ("phi_id:" & Phi_Id'Image (Id) & ", nbr:" & Uns32'Image (Phi.Nbr));
       New_Line;
       Asgn := Phi.First;
-      while Asgn /= No_Assign loop
+      while Asgn /= No_Seq_Assign loop
          Dump_Assign (Asgn);
          Asgn := Get_Assign_Chain (Asgn);
       end loop;
diff --git a/src/synth/synth-environment-debug.ads b/src/synth/synth-environment-debug.ads
index 55bbf3d66..2dd25a930 100644
--- a/src/synth/synth-environment-debug.ads
+++ b/src/synth/synth-environment-debug.ads
@@ -20,6 +20,6 @@
 
 package Synth.Environment.Debug is
    procedure Dump_Wire_Id (Id : Wire_Id);
-   procedure Dump_Assign (Asgn : Assign);
+   procedure Dump_Assign (Asgn : Seq_Assign);
    procedure Dump_Phi (Id : Phi_Id);
 end Synth.Environment.Debug;
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index 6a6229e9f..536ea5710 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -24,22 +24,22 @@ with Netlists.Builders; use Netlists.Builders;
 with Synth.Inference;
 
 package body Synth.Environment is
-   function Get_Wire_Id (W : Assign) return Wire_Id is
+   function Get_Wire_Id (W : Seq_Assign) return Wire_Id is
    begin
       return Assign_Table.Table (W).Id;
    end Get_Wire_Id;
 
-   function Get_Assign_Prev (Asgn : Assign) return Assign is
+   function Get_Assign_Prev (Asgn : Seq_Assign) return Seq_Assign is
    begin
       return Assign_Table.Table (Asgn).Prev;
    end Get_Assign_Prev;
 
-   function Get_Assign_Chain (Asgn : Assign) return Assign is
+   function Get_Assign_Chain (Asgn : Seq_Assign) return Seq_Assign is
    begin
       return Assign_Table.Table (Asgn).Chain;
    end Get_Assign_Chain;
 
-   procedure Set_Assign_Chain (Asgn : Assign; Chain : Assign) is
+   procedure Set_Assign_Chain (Asgn : Seq_Assign; Chain : Seq_Assign) is
    begin
       Assign_Table.Table (Asgn).Chain := Chain;
    end Set_Assign_Chain;
@@ -51,7 +51,7 @@ package body Synth.Environment is
 
    procedure Push_Phi is
    begin
-      Phis_Table.Append ((First => No_Assign,
+      Phis_Table.Append ((First => No_Seq_Assign,
                           Nbr => 0));
    end Push_Phi;
 
@@ -59,7 +59,7 @@ package body Synth.Environment is
    procedure Pop_Phi (Phi : out Phi_Type)
    is
       Cur_Phi : constant Phi_Id := Current_Phi;
-      Asgn : Assign;
+      Asgn : Seq_Assign;
    begin
       --  Pop.
       Phi := Phis_Table.Table (Cur_Phi);
@@ -68,7 +68,7 @@ package body Synth.Environment is
       --  Point to previous wires.  The current values are the ones before
       --  the block.
       Asgn := Phi.First;
-      while Asgn /= No_Assign loop
+      while Asgn /= No_Seq_Assign loop
          pragma Assert (Assign_Table.Table (Asgn).Phi = Cur_Phi);
          Wire_Id_Table.Table (Get_Wire_Id (Asgn)).Cur_Assign :=
            Get_Assign_Prev (Asgn);
@@ -81,14 +81,14 @@ package body Synth.Environment is
    procedure Pop_And_Merge_Phi (Ctxt : Builders.Context_Acc)
    is
       Phi : Phi_Type;
-      Asgn : Assign;
+      Asgn : Seq_Assign;
    begin
       Pop_Phi (Phi);
 
       Asgn := Phi.First;
-      while Asgn /= No_Assign loop
+      while Asgn /= No_Seq_Assign loop
          declare
-            Asgn_Rec : Assign_Record renames Assign_Table.Table (Asgn);
+            Asgn_Rec : Seq_Assign_Record renames Assign_Table.Table (Asgn);
             Outport : constant Net := Wire_Id_Table.Table (Asgn_Rec.Id).Gate;
             --  Must be connected to an Id_Output or Id_Signal
             pragma Assert (Outport /= No_Net);
@@ -140,23 +140,25 @@ package body Synth.Environment is
    --  (the one after LEN) is assigned to NEXT.  The chain headed by FIRST
    --  is truncated to LEN elements.
    --  Use a merge sort.
-   procedure Sort_Wires
-     (Asgn : Assign; Len : Uns32; First : out Assign; Next : out Assign)
+   procedure Sort_Wires (Asgn : Seq_Assign;
+                         Len : Uns32;
+                         First : out Seq_Assign;
+                         Next : out Seq_Assign)
    is
-      Left, Right : Assign;
-      Last : Assign;
-      El : Assign;
+      Left, Right : Seq_Assign;
+      Last : Seq_Assign;
+      El : Seq_Assign;
    begin
       if Len = 0 then
          --  Empty chain.
-         First := No_Assign;
+         First := No_Seq_Assign;
          Next := Asgn;
          return;
       elsif Len = 1 then
          --  Chain with one element.
          First := Asgn;
          Next := Get_Assign_Chain (First);
-         Set_Assign_Chain (First, No_Assign);
+         Set_Assign_Chain (First, No_Seq_Assign);
          return;
       else
          --  Divide.
@@ -164,45 +166,45 @@ package body Synth.Environment is
          Sort_Wires (Right, Len - Len / 2, Right, Next);
 
          --  Conquer: merge.
-         First := No_Assign;
-         Last := No_Assign;
+         First := No_Seq_Assign;
+         Last := No_Seq_Assign;
          for I in 1 .. Len loop
-            if Left /= No_Assign
-              and then (Right = No_Assign
+            if Left /= No_Seq_Assign
+              and then (Right = No_Seq_Assign
                           or else Get_Wire_Id (Left) <= Get_Wire_Id (Right))
             then
                El := Left;
                Left := Get_Assign_Chain (Left);
             else
-               pragma Assert (Right /= No_Assign);
+               pragma Assert (Right /= No_Seq_Assign);
                El := Right;
                Right := Get_Assign_Chain (Right);
             end if;
 
             --  Append
-            if First = No_Assign then
+            if First = No_Seq_Assign then
                First := El;
             else
                Set_Assign_Chain (Last, El);
             end if;
             Last := El;
          end loop;
-         Set_Assign_Chain (Last, No_Assign);
+         Set_Assign_Chain (Last, No_Seq_Assign);
       end if;
    end Sort_Wires;
 
-   function Sort_Phi (P : Phi_Type) return Assign
+   function Sort_Phi (P : Phi_Type) return Seq_Assign
    is
-      Res, Last : Assign;
+      Res, Last : Seq_Assign;
    begin
       Sort_Wires (P.First, P.Nbr, Res, Last);
-      pragma Assert (Last = No_Assign);
+      pragma Assert (Last = No_Seq_Assign);
       return Res;
    end Sort_Phi;
 
-   function Get_Assign_Value (Asgn : Assign) return Net
+   function Get_Assign_Value (Asgn : Seq_Assign) return Net
    is
-      Asgn_Rec : Assign_Record renames Assign_Table.Table (Asgn);
+      Asgn_Rec : Seq_Assign_Record renames Assign_Table.Table (Asgn);
    begin
       case Wire_Id_Table.Table (Asgn_Rec.Id).Kind is
          when Wire_Signal | Wire_Output | Wire_Inout | Wire_Variable =>
@@ -218,7 +220,7 @@ package body Synth.Environment is
    begin
       case Wid_Rec.Kind is
          when Wire_Variable =>
-            if Wid_Rec.Cur_Assign = No_Assign then
+            if Wid_Rec.Cur_Assign = No_Seq_Assign then
                return Wid_Rec.Gate;
             else
                return Assign_Table.Table (Wid_Rec.Cur_Assign).Value;
@@ -234,7 +236,7 @@ package body Synth.Environment is
    is
       Wid_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
    begin
-      if Wid_Rec.Cur_Assign = No_Assign then
+      if Wid_Rec.Cur_Assign = No_Seq_Assign then
          return Wid_Rec.Gate;
       else
          return Get_Assign_Value (Wid_Rec.Cur_Assign);
@@ -246,8 +248,8 @@ package body Synth.Environment is
                          Sel : Net;
                          T, F : Phi_Type)
    is
-      T_Asgns : Assign;
-      F_Asgns : Assign;
+      T_Asgns : Seq_Assign;
+      F_Asgns : Seq_Assign;
       W : Wire_Id;
       Te, Fe : Net;
       Res : Net;
@@ -255,10 +257,10 @@ package body Synth.Environment is
       T_Asgns := Sort_Phi (T);
       F_Asgns := Sort_Phi (F);
 
-      while T_Asgns /= No_Assign or F_Asgns /= No_Assign loop
+      while T_Asgns /= No_Seq_Assign or F_Asgns /= No_Seq_Assign loop
          --  Extract a wire.
-         if T_Asgns = No_Assign
-           or else (F_Asgns /= No_Assign
+         if T_Asgns = No_Seq_Assign
+           or else (F_Asgns /= No_Seq_Assign
                       and then Get_Wire_Id (F_Asgns) < Get_Wire_Id (T_Asgns))
          then
             --  Has an assignment only for the false branch.
@@ -266,8 +268,8 @@ package body Synth.Environment is
             Te := Get_Last_Assigned_Value (W);
             Fe := Get_Assign_Value (F_Asgns);
             F_Asgns := Get_Assign_Chain (F_Asgns);
-         elsif F_Asgns = No_Assign
-           or else (T_Asgns /= No_Assign
+         elsif F_Asgns = No_Seq_Assign
+           or else (T_Asgns /= No_Seq_Assign
                       and then Get_Wire_Id (T_Asgns) < Get_Wire_Id (F_Asgns))
          then
             --  Has an assignment only for the true branch.
@@ -289,12 +291,12 @@ package body Synth.Environment is
       end loop;
    end Merge_Phis;
 
-   procedure Phi_Insert_Assign (Asgn : Assign)
+   procedure Phi_Insert_Assign (Asgn : Seq_Assign)
    is
-      pragma Assert (Asgn /= No_Assign);
-      Asgn_Rec : Assign_Record renames Assign_Table.Table (Asgn);
+      pragma Assert (Asgn /= No_Seq_Assign);
+      Asgn_Rec : Seq_Assign_Record renames Assign_Table.Table (Asgn);
       pragma Assert (Asgn_Rec.Phi = Current_Phi);
-      pragma Assert (Asgn_Rec.Chain = No_Assign);
+      pragma Assert (Asgn_Rec.Chain = No_Seq_Assign);
       P : Phi_Type renames Phis_Table.Table (Phis_Table.Last);
    begin
       --  Chain assignment in the current sequence.
@@ -305,16 +307,16 @@ package body Synth.Environment is
 
    procedure Phi_Assign (Dest : Wire_Id; Val : Net)
    is
-      Cur_Asgn : constant Assign := Wire_Id_Table.Table (Dest).Cur_Assign;
+      Cur_Asgn : constant Seq_Assign := Wire_Id_Table.Table (Dest).Cur_Assign;
    begin
-      if Cur_Asgn = No_Assign
+      if Cur_Asgn = No_Seq_Assign
         or else Assign_Table.Table (Cur_Asgn).Phi < Current_Phi
       then
          --  Never assigned, or first assignment in that level
          Assign_Table.Append ((Phi => Current_Phi,
                               Id => Dest,
                               Prev => Cur_Asgn,
-                              Chain => No_Assign,
+                              Chain => No_Seq_Assign,
                               Value => Val));
          Wire_Id_Table.Table (Dest).Cur_Assign := Assign_Table.Last;
          Phi_Insert_Assign (Assign_Table.Last);
@@ -329,17 +331,17 @@ begin
                           Mark_Flag => False,
                           Decl => Source.No_Syn_Src,
                           Gate => No_Net,
-                          Cur_Assign => No_Assign));
+                          Cur_Assign => No_Seq_Assign));
    pragma Assert (Wire_Id_Table.Last = No_Wire_Id);
 
    Assign_Table.Append ((Phi => No_Phi_Id,
                         Id => No_Wire_Id,
-                        Prev => No_Assign,
-                        Chain => No_Assign,
+                        Prev => No_Seq_Assign,
+                        Chain => No_Seq_Assign,
                         Value => No_Net));
-   pragma Assert (Assign_Table.Last = No_Assign);
+   pragma Assert (Assign_Table.Last = No_Seq_Assign);
 
-   Phis_Table.Append ((First => No_Assign,
+   Phis_Table.Append ((First => No_Seq_Assign,
                        Nbr => 0));
    pragma Assert (Phis_Table.Last = No_Phi_Id);
 end Synth.Environment;
diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads
index 83c1d9866..d40eeb6f6 100644
--- a/src/synth/synth-environment.ads
+++ b/src/synth/synth-environment.ads
@@ -48,8 +48,8 @@ package Synth.Environment is
       Wire_Input, Wire_Output, Wire_Inout
      );
 
-   type Assign is new Uns32;
-   No_Assign : constant Assign := 0;
+   type Seq_Assign is new Uns32;
+   No_Seq_Assign : constant Seq_Assign := 0;
 
    --  A Wire_Id represents a bit or a vector.
    type Wire_Id_Record is record
@@ -68,7 +68,7 @@ package Synth.Environment is
       Gate : Net;
 
       --  Current assignment (if there is one).
-      Cur_Assign : Assign;
+      Cur_Assign : Seq_Assign;
    end record;
 
    --  The current value of WID.  For variables, this is the last assigned
@@ -83,26 +83,26 @@ package Synth.Environment is
    type Phi_Id is new Uns32;
    No_Phi_Id : constant Phi_Id := 0;
 
-   type Assign_Record is record
+   type Seq_Assign_Record is record
       --  Target of the assignment.
       Id : Wire_Id;
 
       --  Assignment is the previous phi context.
-      Prev : Assign;
+      Prev : Seq_Assign;
 
       --  Corresponding phi context for this wire.
       Phi : Phi_Id;
 
       --  Next wire in the phi context.
-      Chain : Assign;
+      Chain : Seq_Assign;
 
       --  Value assigned.
       Value : Net;
    end record;
 
-   function Get_Wire_Id (W : Assign) return Wire_Id;
-   function Get_Assign_Chain (Asgn : Assign) return Assign;
-   function Get_Assign_Value (Asgn : Assign) return Net;
+   function Get_Wire_Id (W : Seq_Assign) return Wire_Id;
+   function Get_Assign_Chain (Asgn : Seq_Assign) return Seq_Assign;
+   function Get_Assign_Value (Asgn : Seq_Assign) return Net;
 
    type Phi_Type is private;
 
@@ -121,7 +121,8 @@ package Synth.Environment is
                          Sel : Net;
                          T, F : Phi_Type);
 
-   function Sort_Phi (P : Phi_Type) return Assign;
+   --  Sort all seq assign of P by wire id.  Used to more easily merge them.
+   function Sort_Phi (P : Phi_Type) return Seq_Assign;
 
    --  In the current phi context, assign VAL to DEST.
    procedure Phi_Assign (Dest : Wire_Id; Val : Net);
@@ -137,14 +138,14 @@ package Synth.Environment is
       Table_Initial => 1024);
 
    package Assign_Table is new Tables
-     (Table_Component_Type => Assign_Record,
-      Table_Index_Type => Assign,
-      Table_Low_Bound => No_Assign,
+     (Table_Component_Type => Seq_Assign_Record,
+      Table_Index_Type => Seq_Assign,
+      Table_Low_Bound => No_Seq_Assign,
       Table_Initial => 1024);
 
 private
    type Phi_Type is record
-      First : Assign;
+      First : Seq_Assign;
       Nbr : Uns32;
    end record;
 
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 3e80ea63e..6fb9e9313 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -370,7 +370,7 @@ package body Synth.Stmts is
      (Choice_Data_Array, Choice_Data_Array_Acc);
 
    type Alternative_Data_Type is record
-      Asgns : Assign;
+      Asgns : Seq_Assign;
       Val : Net;
    end record;
    type Alternative_Data_Array is
@@ -410,13 +410,13 @@ package body Synth.Stmts is
                                         return Natural
    is
       Res : Natural;
-      Asgn : Assign;
+      Asgn : Seq_Assign;
       W : Wire_Id;
    begin
       Res := 0;
       for I in Alts'Range loop
          Asgn := Alts (I).Asgns;
-         while Asgn /= No_Assign loop
+         while Asgn /= No_Seq_Assign loop
             W := Get_Wire_Id (Asgn);
             if not Wire_Id_Table.Table (W).Mark_Flag then
                Res := Res + 1;
@@ -432,13 +432,13 @@ package body Synth.Stmts is
                                  Alts : Alternative_Data_Array)
    is
       Idx : Natural;
-      Asgn : Assign;
+      Asgn : Seq_Assign;
       W : Wire_Id;
    begin
       Idx := Arr'First;
       for I in Alts'Range loop
          Asgn := Alts (I).Asgns;
-         while Asgn /= No_Assign loop
+         while Asgn /= No_Seq_Assign loop
             W := Get_Wire_Id (Asgn);
             if Wire_Id_Table.Table (W).Mark_Flag then
                Arr (Idx) := W;