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authorTristan Gingold <tgingold@free.fr>2019-07-20 21:25:18 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-20 21:26:52 +0200
commite5f5c65f8471071ca52462d81d0cadc2d5c16950 (patch)
tree6fe335f3ef36d79c8e65b64b3424a96bbb1834a5 /src/synth
parent56c7e71ecc72b528b4d246703b3ec406c7432e8a (diff)
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synth: improve output (id_extract).
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/netlists-disp_vhdl.adb18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index c05e1ade2..4e180d7f7 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -508,16 +508,22 @@ package body Netlists.Disp_Vhdl is
when Id_Extract =>
declare
O : constant Net := Get_Output (Inst, 0);
+ I : constant Net := Get_Input_Net (Inst, 0);
Wd : constant Width := Get_Width (O);
Off : constant Uns32 := Get_Param_Uns32 (Inst, 0);
begin
- Disp_Template (" \o0 <= \i0 (", Inst);
- if Wd > 1 then
- Put_Uns32 (Off + Wd - 1);
- Put (" downto ");
+ Disp_Template (" \o0 <= \i0", Inst);
+ if Get_Width (I) > 1 then
+ -- If width is 1, the signal is declared as a scalar and
+ -- therefore cannot be indexed.
+ if Wd > 1 then
+ Disp_Template (" (\n0 downto \n1)", Inst,
+ (0 => Off + Wd - 1, 1 => Off));
+ else
+ Disp_Template (" (\n0)", Inst, (0 => Off));
+ end if;
end if;
- Put_Uns32 (Off);
- Put_Line (");");
+ Put_Line (";");
end;
when Id_Insert =>
declare