| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: rework error handling in file operations | Tristan Gingold | 2023-01-11 | 1 | -1/+1 |
| * | synth: fix memory allocation in predefined function calls | Tristan Gingold | 2023-01-10 | 1 | -0/+3 |
| * | synth: handle indexes in arrays conversion | Tristan Gingold | 2023-01-10 | 1 | -1/+1 |
| * | synth: add support for numeric_std_unsigned add, sub, fix #2286 | tmeissner | 2022-12-26 | 1 | -2/+8 |
| * | synth: add support for to_x01z. Fix #2285 | Tristan Gingold | 2022-12-26 | 1 | -1/+3 |
| * | synth-vhdl_oper: handle more operators. | Tristan Gingold | 2022-11-30 | 1 | -51/+131 |
| * | synth-vhdl_oper: complete rework on predefined functions. | Tristan Gingold | 2022-11-30 | 1 | -644/+570 |
| * | synth-vhdl_oper: refactoring | Tristan Gingold | 2022-11-30 | 1 | -61/+86 |
| * | synth-vhdl_eval(eval_static_predefined_function_call): handle all operations | Tristan Gingold | 2022-11-28 | 1 | -33/+35 |
| * | synth: handle bit/unsigned and bit/signed vhdl 08 operators. | Tristan Gingold | 2022-11-02 | 1 | -12/+36 |
| * | synth: internal refactoring | Tristan Gingold | 2022-10-29 | 1 | -8/+23 |
| * | synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_misc | Tristan Gingold | 2022-10-19 | 1 | -16/+34 |
| * | synth-vhdl_oper: handle and_reduce. Fix #2224 | Tristan Gingold | 2022-10-19 | 1 | -1/+10 |
| * | synth: rework error procedure, always pass the instance | Tristan Gingold | 2022-09-25 | 1 | -20/+34 |
| * | synth-vhdl_stmts: minor renaming | Tristan Gingold | 2022-09-18 | 1 | -1/+1 |
| * | synth: improve handling of top-level interfaces subtype | Tristan Gingold | 2022-09-11 | 1 | -4/+8 |
| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 1 | -4/+13 |
| * | synth: factorize code for synth_subtype_conversion | Tristan Gingold | 2022-08-21 | 1 | -7/+9 |
| * | synth-vhdl_oper.adb: fix mul uns uns. Fix #2169 | Tristan Gingold | 2022-08-10 | 1 | -1/+1 |
| * | synth-vhdl_oper: remove check for positive rotation amount. Fix #2159 | Tristan Gingold | 2022-08-04 | 1 | -3/+1 |
| * | synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129 | Tristan Gingold | 2022-07-06 | 1 | -1/+3 |
| * | Fix issue #2126, add handling of to_ux01 to synthesis | Michael Nolan | 2022-07-05 | 1 | -1/+3 |
| * | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 1 | -2/+2 |
| * | synth-vhdl_oper: handle more bit_vector operations. Fix #2074 | Tristan Gingold | 2022-06-05 | 1 | -8/+13 |
| * | synth-vhdl_oper: add hooks for bit edge | Tristan Gingold | 2022-05-30 | 1 | -0/+12 |
| * | vhdl-nodes: move maximum/minimum out of predefined operator range | Tristan Gingold | 2022-05-30 | 1 | -18/+21 |
| * | synth-vhdl_oper: add hook for falling edge, handle aliases. | Tristan Gingold | 2022-05-29 | 1 | -0/+4 |
| * | synth-vhdl_oper: add an hook for rising_edge | Tristan Gingold | 2022-05-23 | 1 | -0/+4 |
| * | synth: use same elements for unbounded arrays and vectors | Tristan Gingold | 2022-05-22 | 1 | -3/+3 |
| * | synth: merge value for type_vector and type_array | Tristan Gingold | 2022-05-22 | 1 | -16/+16 |
| * | synth: use unidimentional arrays in type_acc. Factorize code. | Tristan Gingold | 2022-05-22 | 1 | -4/+4 |
| * | synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062 | Tristan Gingold | 2022-05-17 | 1 | -0/+1 |
| * | synth: renaming (synth-static_oper -> synth-vhdl_eval) | Tristan Gingold | 2022-04-27 | 1 | -4/+4 |
| * | synth: abstract code for reuse by evaluation | Tristan Gingold | 2022-04-26 | 1 | -1/+1 |
| * | synth-static_oper: fully remove dependency on synth_instance | Tristan Gingold | 2022-04-26 | 1 | -8/+35 |
| * | synth-static_oper: do not depend on instance for static operations. | Tristan Gingold | 2022-04-26 | 1 | -29/+5 |
| * | synth: handle concatenation of unbounded types. Fix #1993 | Tristan Gingold | 2022-03-08 | 1 | -8/+25 |
| * | synth-vhdl_oper: implement <= for arrays. Fix #1991 | Tristan Gingold | 2022-03-02 | 1 | -7/+17 |
| * | synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977 | Tristan Gingold | 2022-02-17 | 1 | -27/+30 |
| * | synth-vhdl_oper: handle bit condition operator. Fix #1971 | Tristan Gingold | 2022-02-16 | 1 | -1/+2 |
| * | synth: fix handling of std_logic_unsigned."-" for negative numbers. | Tristan Gingold | 2022-01-18 | 1 | -8/+12 |
| * | synth: also handle rol. For #1909 | Tristan Gingold | 2021-11-11 | 1 | -0/+5 |
| * | synth: handle ror from numeric_std. Fix #1909 | Tristan Gingold | 2021-11-11 | 1 | -1/+4 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -1/+4 |
| * | synth-vhdl_oper: handle nor for boolean | Tristan Gingold | 2021-09-14 | 1 | -0/+1 |
| * | synth: add build2_concat2 and use it for vhdl concat. | Tristan Gingold | 2021-08-28 | 1 | -4/+4 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -2/+2 |
| * | synth-vhdl_oper.adb: handle resize uns/uns. For #1731 | Tristan Gingold | 2021-04-21 | 1 | -0/+12 |
| * | synth-vhdl_oper.adb: adjust previous patch and test | Tristan Gingold | 2021-04-21 | 1 | -1/+12 |
| * | synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731 | Tristan Gingold | 2021-04-21 | 1 | -0/+1 |
