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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:25:07 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:25:07 +0100 |
| commit | 5b458e22f3054e64e231160cb91370da63ff1640 (patch) | |
| tree | 4341f6a8861741bb972da91d038fb2acaa2ead1a /src/synth/synth-vhdl_oper.adb | |
| parent | 291a8d4048e513270312afe5d7c3ca930f634724 (diff) | |
| download | ghdl-5b458e22f3054e64e231160cb91370da63ff1640.tar.gz ghdl-5b458e22f3054e64e231160cb91370da63ff1640.tar.bz2 ghdl-5b458e22f3054e64e231160cb91370da63ff1640.zip | |
synth: rework error handling in file operations
Diffstat (limited to 'src/synth/synth-vhdl_oper.adb')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 9063e84c4..206faf1a6 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1965,7 +1965,7 @@ package body Synth.Vhdl_Oper is declare Res : Boolean; begin - Res := Elab.Vhdl_Files.Endfile (L.Val.File, Expr); + Res := Elab.Vhdl_Files.Endfile (Syn_Inst, L.Val.File, Expr); return Create_Value_Memtyp (Create_Memory_U8 (Boolean'Pos (Res), Boolean_Type)); exception |