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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-11 05:06:27 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-11 05:06:27 +0100 |
| commit | ea5b2080161b28544b32797f2a21afca64d2f185 (patch) | |
| tree | 850132a925ed8d934ba53a4dbcac49b91f037b9f /src/synth/synth-vhdl_oper.adb | |
| parent | 6dcda18bb1e363cbd07ead329b3caf7f1467b9bc (diff) | |
| download | ghdl-ea5b2080161b28544b32797f2a21afca64d2f185.tar.gz ghdl-ea5b2080161b28544b32797f2a21afca64d2f185.tar.bz2 ghdl-ea5b2080161b28544b32797f2a21afca64d2f185.zip | |
synth: handle ror from numeric_std. Fix #1909
Diffstat (limited to 'src/synth/synth-vhdl_oper.adb')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index c576f2fee..ee30c84d4 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1587,6 +1587,7 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Uns => -- ">=" (Signed, Unsigned) return Synth_Compare_Sgn_Uns (Id_Sge, Expr_Typ); + when Iir_Predefined_Ieee_Numeric_Std_Sra_Sgn_Int => return Synth_Shift (Id_Asr, Id_Lsl); @@ -1600,7 +1601,9 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_1164_Vector_Srl => return Synth_Shift (Id_Lsr, Id_Lsl); - when Iir_Predefined_Ieee_1164_Vector_Ror => + when Iir_Predefined_Ieee_Numeric_Std_Ror_Uns_Int + | Iir_Predefined_Ieee_Numeric_Std_Ror_Sgn_Int + | Iir_Predefined_Ieee_1164_Vector_Ror => return Synth_Rotation (Id_Ror); when others => |