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| author | Tristan Gingold <tgingold@free.fr> | 2022-01-18 06:52:53 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-01-18 06:52:53 +0100 |
| commit | c22b2f1586880a495f2f027193f9265e82552302 (patch) | |
| tree | 45eaf20a3accb3d899c4b5bf2c0900220fceb525 /src/synth/synth-vhdl_oper.adb | |
| parent | 25ccaf3d801734f6209f8ebeeac8d265c89313b5 (diff) | |
| download | ghdl-c22b2f1586880a495f2f027193f9265e82552302.tar.gz ghdl-c22b2f1586880a495f2f027193f9265e82552302.tar.bz2 ghdl-c22b2f1586880a495f2f027193f9265e82552302.zip | |
synth: fix handling of std_logic_unsigned."-" for negative numbers.
Fix #1951
Diffstat (limited to 'src/synth/synth-vhdl_oper.adb')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index e725b3ed6..e6221075d 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1118,12 +1118,14 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Ctxt, Id_Add, Left, Right, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Uns - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat => -- "+" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Add, Left, Right, Expr); + when Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => + -- "+" (Unsigned, Integer) + return Synth_Dyadic_Sgn_Int (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv @@ -1184,12 +1186,14 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv => -- "-" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, Left, Right, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, Left, Right, Expr); + when Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => + -- "-" (Unsigned, Integer) + return Synth_Dyadic_Sgn_Int (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv |