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synth
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synth-decls.adb
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Author
Age
Files
Lines
*
synth: preliminary support of integer subtypes.
Tristan Gingold
2019-07-26
1
-1
/
+1
*
synth: handle bit.
Tristan Gingold
2019-07-25
1
-0
/
+1
*
synth: save and display locations for instances.
Tristan Gingold
2019-07-25
1
-0
/
+1
*
synth: handle record type declarations.
Tristan Gingold
2019-07-24
1
-1
/
+11
*
synth: make type Wire_Id_Record private.
Tristan Gingold
2019-07-17
1
-1
/
+1
*
synth: handle anonymous subtypes in array subtypes.
Tristan Gingold
2019-07-15
1
-4
/
+10
*
synth: do not crash on use of std_logic_1164 2008.
Tristan Gingold
2019-07-10
1
-2
/
+6
*
vhdl-annotations: partial revert of previous patch for
Tristan Gingold
2019-07-04
1
-1
/
+2
*
synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.
Tristan Gingold
2019-07-04
1
-5
/
+6
*
synth: ignore non object aliases.
Tristan Gingold
2019-07-03
1
-0
/
+2
*
synth-decls: handle initial value for variables and
Tristan Gingold
2019-07-02
1
-5
/
+4
*
synth: destroy iterator after for-loop.
Tristan Gingold
2019-07-01
1
-7
/
+16
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
1
-1
/
+1
*
synth: get rid of execution and elaboration.
Tristan Gingold
2019-06-19
1
-13
/
+185
*
synth: handle enumerated types.
Tristan Gingold
2019-06-12
1
-4
/
+38
*
synth: handle integer +/- for constants.
Tristan Gingold
2019-06-08
1
-0
/
+2
*
synth: WIP for dependencies.
Tristan Gingold
2019-06-07
1
-0
/
+7
*
synth: add comments and refactoring.
Tristan Gingold
2019-06-07
1
-1
/
+1
*
synth: ignore attribute specifications
Christos Gentsos
2019-06-06
1
-0
/
+2
*
synth-decls: ignore attribute declarations
Christos Gentsos
2019-06-06
1
-0
/
+2
*
synth: add support for constants.
Pepijn de Vos
2019-05-28
1
-0
/
+2
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-1
/
+1
*
Create the simul.ads package (for a namespace).
Tristan Gingold
2017-11-24
1
-2
/
+2
*
Add netlist generation infrastructure.
Tristan Gingold
2017-01-31
1
-0
/
+116