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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:12 +0200 |
| commit | 86a35becd584aaa8d09ce1e677c363dd66a40774 (patch) | |
| tree | 21cd58f1c63a94ef23bd805b7f09016574401d70 /src/synth/synth-decls.adb | |
| parent | 82e5fc7bf210aa3339ac347e921f4b941af7d827 (diff) | |
| download | ghdl-86a35becd584aaa8d09ce1e677c363dd66a40774.tar.gz ghdl-86a35becd584aaa8d09ce1e677c363dd66a40774.tar.bz2 ghdl-86a35becd584aaa8d09ce1e677c363dd66a40774.zip | |
synth-decls: handle initial value for variables and
Diffstat (limited to 'src/synth/synth-decls.adb')
| -rw-r--r-- | src/synth/synth-decls.adb | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 0166a07b8..a4668cf70 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -275,8 +275,8 @@ package body Synth.Decls is begin Make_Object (Syn_Inst, Wire_Variable, Decl); if Is_Valid (Def) then - -- TODO. - raise Internal_Error; + Init := Synth_Expression_With_Type + (Syn_Inst, Def, Get_Type (Decl)); else Init := null; end if; @@ -297,9 +297,8 @@ package body Synth.Decls is begin Make_Object (Syn_Inst, Wire_Signal, Decl); if Is_Valid (Def) then - -- TODO. - raise Internal_Error; - -- Init := Syn_Inst.Sim.Objects (Slot + 1); + Init := Synth_Expression_With_Type + (Syn_Inst, Def, Get_Type (Decl)); else Init := null; end if; |