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synth
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netlists-gates.ads
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Author
Age
Files
Lines
*
synth: preliminary support of multiport rams (using shared variable).
Tristan Gingold
2020-03-28
1
-0
/
+3
*
netlists-gates: improve comments.
Tristan Gingold
2020-03-26
1
-1
/
+4
*
synth: add id_inout gate to handle inout behaviour. Fir #1166
Tristan Gingold
2020-03-23
1
-0
/
+12
*
synth-disp_vhdl: do not wrap inout ports. For #1166
Tristan Gingold
2020-03-22
1
-0
/
+1
*
netlists: add id_nop gate.
Tristan Gingold
2020-03-22
1
-0
/
+3
*
synth: handle numeric_std minimum/maximum. Fix #1168
Tristan Gingold
2020-03-21
1
-44
/
+48
*
synthesis: handle initialized output ports.
Tristan Gingold
2020-03-07
1
-7
/
+9
*
netlists: add midff
Tristan Gingold
2020-02-20
1
-0
/
+8
*
synth: add mdff.
Tristan Gingold
2020-02-17
1
-0
/
+8
*
synth: add id_abs gate. For #1101
Tristan Gingold
2020-01-20
1
-10
/
+11
*
netlists-disp_vhdl: display iadff.
Tristan Gingold
2019-12-31
1
-6
/
+13
*
synth: add minor comments.
Tristan Gingold
2019-12-23
1
-0
/
+2
*
synth: add Get_Input_Instance.
Tristan Gingold
2019-12-14
1
-0
/
+2
*
netlists-gates: add comments.
Tristan Gingold
2019-12-05
1
-3
/
+13
*
netlists-gates: add comments.
Tristan Gingold
2019-11-11
1
-0
/
+3
*
netlists: add more support for dyn_insert_en
Tristan Gingold
2019-11-11
1
-0
/
+3
*
netlists: add dyn_insert_en gate.
Tristan Gingold
2019-11-11
1
-17
/
+21
*
netlists-expands: expand dyn_insert
Tristan Gingold
2019-11-01
1
-0
/
+3
*
netlists: add formal input gates.
Tristan Gingold
2019-10-30
1
-0
/
+8
*
synth: generate cover for assertion precedent.
Tristan Gingold
2019-10-21
1
-0
/
+4
*
synth: add netlists-memories to extract memories. Still WIP.
Tristan Gingold
2019-10-17
1
-0
/
+1
*
netlists: declare memory gates.
Tristan Gingold
2019-10-15
1
-0
/
+36
*
netlists: rename id_memidx1 to id_memidx
Tristan Gingold
2019-10-03
1
-1
/
+1
*
synth: replace memidx2 by addidx; handle some 2d arrays.
Tristan Gingold
2019-10-03
1
-2
/
+2
*
synth: simplify dyn_insert.
Tristan Gingold
2019-10-02
1
-1
/
+1
*
synth: simplify id_dyn_extract.
Tristan Gingold
2019-10-02
1
-1
/
+1
*
synth: introduce memidx1
Tristan Gingold
2019-10-02
1
-1
/
+1
*
netlists: add memidx1 and memidx2 gates.
Tristan Gingold
2019-10-02
1
-4
/
+10
*
netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.
Tristan Gingold
2019-10-02
1
-0
/
+3
*
synth: add support for integer rem.
Tristan Gingold
2019-10-01
1
-1
/
+2
*
synth: improve support of * and /. Fix #953
Tristan Gingold
2019-09-30
1
-2
/
+4
*
synth: add support for mod operator.
Tristan Gingold
2019-09-28
1
-20
/
+22
*
synth: handle rotate.
Tristan Gingold
2019-09-22
1
-26
/
+34
*
synth: use constant for constant values.
Tristan Gingold
2019-09-21
1
-0
/
+2
*
synth: Add support for PSL cover directive (#930)
T. Meissner
2019-09-19
1
-0
/
+1
*
synth-inference: detect false loop.
Tristan Gingold
2019-09-17
1
-0
/
+2
*
synth: minor refactoring about const gates.
Tristan Gingold
2019-09-15
1
-0
/
+9
*
synth: handle unsigned shift left.
Tristan Gingold
2019-09-11
1
-53
/
+57
*
synth: add const_x gate.
Tristan Gingold
2019-09-11
1
-0
/
+1
*
synth: add const_sb32, add smul/umul.
Tristan Gingold
2019-09-07
1
-2
/
+4
*
synth: remove insert gate.
Tristan Gingold
2019-08-31
1
-7
/
+0
*
synth: remove unused const gates.
Tristan Gingold
2019-08-30
1
-7
/
+2
*
synth: add support for memories.
Tristan Gingold
2019-07-29
1
-1
/
+5
*
synth: add concatn gate
Tristan Gingold
2019-07-19
1
-0
/
+3
*
synth: add const_z gate.
Tristan Gingold
2019-07-19
1
-0
/
+2
*
synth: add Id_Port gate to improve display.
Tristan Gingold
2019-07-10
1
-23
/
+24
*
netlists: add reduce_or/reduce_and gates.
Tristan Gingold
2019-07-04
1
-0
/
+2
*
netlists: add assume gate.
Tristan Gingold
2019-07-04
1
-0
/
+1
*
synth: handle concurrent assertions.
Tristan Gingold
2019-07-02
1
-0
/
+3
*
synth: add dyn_insert module.
Tristan Gingold
2019-07-01
1
-4
/
+10
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