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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-17 06:35:04 +0200 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-17 06:35:04 +0200 |
| commit | a87efba0ca0cc55cc26a28371eb1963a2e720498 (patch) | |
| tree | a0d18b5bb7b1b3304599ddd35a189ea1c5f138a4 /src/synth/netlists-gates.ads | |
| parent | cb024436717e81efcb6cefb7f1c16ecb86e21afa (diff) | |
| download | ghdl-a87efba0ca0cc55cc26a28371eb1963a2e720498.tar.gz ghdl-a87efba0ca0cc55cc26a28371eb1963a2e720498.tar.bz2 ghdl-a87efba0ca0cc55cc26a28371eb1963a2e720498.zip | |
synth: add netlists-memories to extract memories. Still WIP.
Diffstat (limited to 'src/synth/netlists-gates.ads')
| -rw-r--r-- | src/synth/netlists-gates.ads | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index f37b41f67..e0cf9a6e1 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -169,6 +169,7 @@ package Netlists.Gates is Id_Memory : constant Module_Id := 73; -- Same as Id_Memory but with an initial value. + -- Input: INIT Id_Memory_Init : constant Module_Id := 74; -- Asynchronous memory read port. |