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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-01 07:50:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-01 07:50:12 +0200 |
| commit | 410178f09ab8718d36ce04acbaa19946575fcacb (patch) | |
| tree | c47b49354a5a3da76446b06c9d6fcc207d6f1248 /src/synth/netlists-gates.ads | |
| parent | 4202d78df0bb056f3036b5c9bc789a10148a22c8 (diff) | |
| download | ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.tar.gz ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.tar.bz2 ghdl-410178f09ab8718d36ce04acbaa19946575fcacb.zip | |
synth: add support for integer rem.
Diffstat (limited to 'src/synth/netlists-gates.ads')
| -rw-r--r-- | src/synth/netlists-gates.ads | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index f45313e10..9e9260808 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -39,8 +39,9 @@ package Netlists.Gates is Id_Sdiv : constant Module_Id := 14; Id_Umod : constant Module_Id := 15; Id_Smod : constant Module_Id := 16; + Id_Srem : constant Module_Id := 17; - subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Smod; + subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Srem; -- Logical and arithmetic shifts. -- FIXME: clarify right operand: width, large values |