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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-21 20:31:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-21 20:31:47 +0200 |
| commit | 642c8abe2155fad9ce0d5ba830d603270b24f55d (patch) | |
| tree | ff2e02a09a15cf0ec0a44cd0642c189e9d506691 /src/synth/netlists-gates.ads | |
| parent | 9c4519e0c72187f95b6a91e95564ee6a1f45efc7 (diff) | |
| download | ghdl-642c8abe2155fad9ce0d5ba830d603270b24f55d.tar.gz ghdl-642c8abe2155fad9ce0d5ba830d603270b24f55d.tar.bz2 ghdl-642c8abe2155fad9ce0d5ba830d603270b24f55d.zip | |
synth: generate cover for assertion precedent.
Diffstat (limited to 'src/synth/netlists-gates.ads')
| -rw-r--r-- | src/synth/netlists-gates.ads | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index e0cf9a6e1..ae6c2f58d 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -204,7 +204,11 @@ package Netlists.Gates is -- Input signal must always be true. Id_Assert : constant Module_Id := 81; Id_Assume : constant Module_Id := 82; + + -- Input is true when a sequence is covered. Id_Cover : constant Module_Id := 83; + -- Use to cover the precedent of an assertion. + Id_Assert_Cover : constant Module_Id := 84; -- Constants are gates with only one constant output. There are multiple -- kind of constant gates: for small width, the value is stored as a |