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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-02 18:38:40 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-02 18:38:40 +0200 |
| commit | 336dbeaa305bdfe968a500161f561b35a9c495c0 (patch) | |
| tree | 4a56436f5e17ba6fd7b62d4507d3c8a725492767 /src/synth/netlists-gates.ads | |
| parent | bfad2a487e2e6f6476e9417d70dff73656041883 (diff) | |
| download | ghdl-336dbeaa305bdfe968a500161f561b35a9c495c0.tar.gz ghdl-336dbeaa305bdfe968a500161f561b35a9c495c0.tar.bz2 ghdl-336dbeaa305bdfe968a500161f561b35a9c495c0.zip | |
netlists: add memidx1 and memidx2 gates.
Diffstat (limited to 'src/synth/netlists-gates.ads')
| -rw-r--r-- | src/synth/netlists-gates.ads | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 1379c038d..41cb597f6 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -153,15 +153,21 @@ package Netlists.Gates is -- OUT := T Id_Dyn_Insert : constant Module_Id := 70; + -- OUT := IN0 * STEP, IN0 < MAX + Id_Memidx1 : constant Module_Id := 71; + + -- OUT := IN0 * STEP + IN1, IN0 < MAX + Id_Memidx2 : constant Module_Id := 72; + -- Positive/rising edge detector. This is a pseudo gate. -- A negative edge detector can be made using by negating the clock before -- the detector. - Id_Edge : constant Module_Id := 71; + Id_Edge : constant Module_Id := 80; -- Input signal must always be true. - Id_Assert : constant Module_Id := 72; - Id_Assume : constant Module_Id := 73; - Id_Cover : constant Module_Id := 74; + Id_Assert : constant Module_Id := 81; + Id_Assume : constant Module_Id := 82; + Id_Cover : constant Module_Id := 83; -- Constants are gates with only one constant output. There are multiple -- kind of constant gates: for small width, the value is stored as a |