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* update license headersumarcor2021-02-051-5/+3
* netlists-inference: handle multiple dff with the same clock. Fix #1563Tristan Gingold2021-01-011-0/+2
* synth: fix handling of multi-dim ROM. Fix #1390Tristan Gingold2020-07-241-0/+9
* netlists-gates.ads: add comments.Tristan Gingold2020-06-021-6/+8
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-8/+9
* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-151-10/+14
* netlists-gates: reserve pmux and latch.Tristan Gingold2020-05-091-51/+60
* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-061-0/+3
* netlists-memories: Handle gated dyn_extract.Tristan Gingold2020-04-261-5/+5
* synth: add tri gate.Tristan Gingold2020-04-221-1/+20
* synth: rework edge handling to properly support falling edge. Fix #1227Tristan Gingold2020-04-151-8/+9
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-0/+3
* netlists-gates: improve comments.Tristan Gingold2020-03-261-1/+4
* synth: add id_inout gate to handle inout behaviour. Fir #1166Tristan Gingold2020-03-231-0/+12
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-0/+1
* netlists: add id_nop gate.Tristan Gingold2020-03-221-0/+3
* synth: handle numeric_std minimum/maximum. Fix #1168Tristan Gingold2020-03-211-44/+48
* synthesis: handle initialized output ports.Tristan Gingold2020-03-071-7/+9
* netlists: add midffTristan Gingold2020-02-201-0/+8
* synth: add mdff.Tristan Gingold2020-02-171-0/+8
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-10/+11
* netlists-disp_vhdl: display iadff.Tristan Gingold2019-12-311-6/+13
* synth: add minor comments.Tristan Gingold2019-12-231-0/+2
* synth: add Get_Input_Instance.Tristan Gingold2019-12-141-0/+2
* netlists-gates: add comments.Tristan Gingold2019-12-051-3/+13
* netlists-gates: add comments.Tristan Gingold2019-11-111-0/+3
* netlists: add more support for dyn_insert_enTristan Gingold2019-11-111-0/+3
* netlists: add dyn_insert_en gate.Tristan Gingold2019-11-111-17/+21
* netlists-expands: expand dyn_insertTristan Gingold2019-11-011-0/+3
* netlists: add formal input gates.Tristan Gingold2019-10-301-0/+8
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-211-0/+4
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-171-0/+1
* netlists: declare memory gates.Tristan Gingold2019-10-151-0/+36
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-1/+1
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-2/+2
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-1/+1
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-1/+1
* synth: introduce memidx1Tristan Gingold2019-10-021-1/+1
* netlists: add memidx1 and memidx2 gates.Tristan Gingold2019-10-021-4/+10
* netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.Tristan Gingold2019-10-021-0/+3
* synth: add support for integer rem.Tristan Gingold2019-10-011-1/+2
* synth: improve support of * and /. Fix #953Tristan Gingold2019-09-301-2/+4
* synth: add support for mod operator.Tristan Gingold2019-09-281-20/+22
* synth: handle rotate.Tristan Gingold2019-09-221-26/+34
* synth: use constant for constant values.Tristan Gingold2019-09-211-0/+2
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+1
* synth-inference: detect false loop.Tristan Gingold2019-09-171-0/+2
* synth: minor refactoring about const gates.Tristan Gingold2019-09-151-0/+9
* synth: handle unsigned shift left.Tristan Gingold2019-09-111-53/+57
* synth: add const_x gate.Tristan Gingold2019-09-111-0/+1
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