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path: root/src/synth/netlists-disp_vhdl.adb
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* netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.Tristan Gingold2019-10-041-0/+18
* netlists-disp_vhdl: add qualification when needed for =Tristan Gingold2019-10-041-5/+24
* netlists-disp_vhdl: handle empty operand for concat2, addTristan Gingold2019-10-041-1/+30
* netlists-disp_vhdl: handle id_negTristan Gingold2019-10-041-0/+2
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-1/+1
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-3/+28
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-3/+3
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-8/+1
* synth: introduce memidx1Tristan Gingold2019-10-021-0/+15
* netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.Tristan Gingold2019-10-021-1/+22
* netlists-disp_vhdl: display constant signals connected to user submodules.Tristan Gingold2019-10-011-0/+2
* synth: add support for integer rem.Tristan Gingold2019-10-011-0/+6
* netlists-disp_vhdl: improve disp_x_lit.Tristan Gingold2019-09-281-3/+9
* netlists-disp_vhdl: handle id_edge.Tristan Gingold2019-09-281-0/+3
* synth: fix handling of single-bit memories.Tristan Gingold2019-09-261-4/+11
* netlists-disp_vhdl: handle lsr.Tristan Gingold2019-09-211-0/+4
* synth: use constant for constant values.Tristan Gingold2019-09-211-30/+62
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+4
* synth: minor refactoring about const gates.Tristan Gingold2019-09-151-36/+22
* synth: add const_x gate.Tristan Gingold2019-09-111-1/+5
* synth: introduce slice type.Tristan Gingold2019-09-111-0/+4
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-1/+1
* synth: handle const_bit in disp_constant_inline.Tristan Gingold2019-09-041-0/+4
* synth: remove insert gate.Tristan Gingold2019-08-311-22/+0
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* synth: set name to assert/assume gates.Tristan Gingold2019-08-201-2/+8
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-201-0/+13
* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-011-0/+12
* synth: adjust output for dyn_insert, add dpram2 test.Tristan Gingold2019-07-301-2/+2
* synth: fixes for indexed names.Tristan Gingold2019-07-301-1/+1
* synth: add support for memories.Tristan Gingold2019-07-291-6/+58
* synth: save and display locations for instances.Tristan Gingold2019-07-251-0/+20
* synth: fix incorrect slice in disp_vhdl for Insert.Tristan Gingold2019-07-251-6/+1
* synth: use original entity to display netlist.Tristan Gingold2019-07-231-18/+30
* synth: minor refactoring in netlists.disp_vhdlTristan Gingold2019-07-221-47/+51
* synth: rework names.Tristan Gingold2019-07-221-18/+10
* synth: improve output (id_extract).Tristan Gingold2019-07-201-6/+12
* synth: improve output (for id_insert).Tristan Gingold2019-07-201-11/+18
* synth: add concatn gateTristan Gingold2019-07-191-3/+14
* synth: add const_z gate.Tristan Gingold2019-07-191-1/+5
* synth: add > and >= operators (#870)Pepijn de Vos2019-07-161-0/+6
* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-101-1/+21
* synth: display instances in reverse order.Tristan Gingold2019-07-101-5/+28
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-8/+19
* netlists-disp_vhdl: display initial value of idff.Tristan Gingold2019-07-041-19/+32
* netlists: add reduce_or/reduce_and gates.Tristan Gingold2019-07-041-0/+13
* netlists: add assume gate.Tristan Gingold2019-07-041-0/+3
* synth: handle concurrent assertions.Tristan Gingold2019-07-021-0/+2
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