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synth
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netlists-disp_vhdl.adb
Commit message (
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Author
Age
Files
Lines
*
netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.
Tristan Gingold
2019-10-04
1
-0
/
+18
*
netlists-disp_vhdl: add qualification when needed for =
Tristan Gingold
2019-10-04
1
-5
/
+24
*
netlists-disp_vhdl: handle empty operand for concat2, add
Tristan Gingold
2019-10-04
1
-1
/
+30
*
netlists-disp_vhdl: handle id_neg
Tristan Gingold
2019-10-04
1
-0
/
+2
*
netlists: rename id_memidx1 to id_memidx
Tristan Gingold
2019-10-03
1
-1
/
+1
*
synth: replace memidx2 by addidx; handle some 2d arrays.
Tristan Gingold
2019-10-03
1
-3
/
+28
*
synth: simplify dyn_insert.
Tristan Gingold
2019-10-02
1
-3
/
+3
*
synth: simplify id_dyn_extract.
Tristan Gingold
2019-10-02
1
-8
/
+1
*
synth: introduce memidx1
Tristan Gingold
2019-10-02
1
-0
/
+15
*
netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.
Tristan Gingold
2019-10-02
1
-1
/
+22
*
netlists-disp_vhdl: display constant signals connected to user submodules.
Tristan Gingold
2019-10-01
1
-0
/
+2
*
synth: add support for integer rem.
Tristan Gingold
2019-10-01
1
-0
/
+6
*
netlists-disp_vhdl: improve disp_x_lit.
Tristan Gingold
2019-09-28
1
-3
/
+9
*
netlists-disp_vhdl: handle id_edge.
Tristan Gingold
2019-09-28
1
-0
/
+3
*
synth: fix handling of single-bit memories.
Tristan Gingold
2019-09-26
1
-4
/
+11
*
netlists-disp_vhdl: handle lsr.
Tristan Gingold
2019-09-21
1
-0
/
+4
*
synth: use constant for constant values.
Tristan Gingold
2019-09-21
1
-30
/
+62
*
synth: Add support for PSL cover directive (#930)
T. Meissner
2019-09-19
1
-0
/
+4
*
synth: minor refactoring about const gates.
Tristan Gingold
2019-09-15
1
-36
/
+22
*
synth: add const_x gate.
Tristan Gingold
2019-09-11
1
-1
/
+5
*
synth: introduce slice type.
Tristan Gingold
2019-09-11
1
-0
/
+4
*
synth: add const_sb32, add smul/umul.
Tristan Gingold
2019-09-07
1
-1
/
+1
*
synth: handle const_bit in disp_constant_inline.
Tristan Gingold
2019-09-04
1
-0
/
+4
*
synth: remove insert gate.
Tristan Gingold
2019-08-31
1
-22
/
+0
*
netlists-disp_vhdl: do not used literals for prefixes.
Tristan Gingold
2019-08-27
1
-12
/
+53
*
synth: set name to assert/assume gates.
Tristan Gingold
2019-08-20
1
-2
/
+8
*
netlist: fix minor pasto.
Tristan Gingold
2019-08-20
1
-1
/
+1
*
initial support for reduce and/or (#900)
Pepijn de Vos
2019-08-20
1
-0
/
+13
*
synth: handle signed conversions in disp_vhdl.
Tristan Gingold
2019-08-05
1
-2
/
+6
*
synth: handle signed integer comparisons (#878)
Pepijn de Vos
2019-08-01
1
-0
/
+12
*
synth: adjust output for dyn_insert, add dpram2 test.
Tristan Gingold
2019-07-30
1
-2
/
+2
*
synth: fixes for indexed names.
Tristan Gingold
2019-07-30
1
-1
/
+1
*
synth: add support for memories.
Tristan Gingold
2019-07-29
1
-6
/
+58
*
synth: save and display locations for instances.
Tristan Gingold
2019-07-25
1
-0
/
+20
*
synth: fix incorrect slice in disp_vhdl for Insert.
Tristan Gingold
2019-07-25
1
-6
/
+1
*
synth: use original entity to display netlist.
Tristan Gingold
2019-07-23
1
-18
/
+30
*
synth: minor refactoring in netlists.disp_vhdl
Tristan Gingold
2019-07-22
1
-47
/
+51
*
synth: rework names.
Tristan Gingold
2019-07-22
1
-18
/
+10
*
synth: improve output (id_extract).
Tristan Gingold
2019-07-20
1
-6
/
+12
*
synth: improve output (for id_insert).
Tristan Gingold
2019-07-20
1
-11
/
+18
*
synth: add concatn gate
Tristan Gingold
2019-07-19
1
-3
/
+14
*
synth: add const_z gate.
Tristan Gingold
2019-07-19
1
-1
/
+5
*
synth: add > and >= operators (#870)
Pepijn de Vos
2019-07-16
1
-0
/
+6
*
synth: add Id_Port gate to improve display.
Tristan Gingold
2019-07-10
1
-1
/
+21
*
synth: display instances in reverse order.
Tristan Gingold
2019-07-10
1
-5
/
+28
*
synth: handle instantiation (WIP)
Tristan Gingold
2019-07-10
1
-8
/
+19
*
netlists-disp_vhdl: display initial value of idff.
Tristan Gingold
2019-07-04
1
-19
/
+32
*
netlists: add reduce_or/reduce_and gates.
Tristan Gingold
2019-07-04
1
-0
/
+13
*
netlists: add assume gate.
Tristan Gingold
2019-07-04
1
-0
/
+3
*
synth: handle concurrent assertions.
Tristan Gingold
2019-07-02
1
-0
/
+2
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