Commit message (Collapse) | Author | Age | Files | Lines | |
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* | synth: make more types private. | Tristan Gingold | 2019-07-17 | 2 | -35/+48 |
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* | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 7 | -44/+74 |
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* | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 6 | -79/+82 |
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* | synth: add comments. | Tristan Gingold | 2019-07-17 | 2 | -0/+2 |
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* | Add a testcase about distinct alternate labels. | Tristan Gingold | 2019-07-16 | 3 | -0/+145 |
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* | vhdl: add a comment. | Tristan Gingold | 2019-07-16 | 1 | -0/+3 |
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* | synth: add > and >= operators (#870) | Pepijn de Vos | 2019-07-16 | 6 | -25/+118 |
| | | | | | | * synth: add > and >= operators * synth: update ghdlsynth_gates.h | ||||
* | Add testcase for #869 | Tristan Gingold | 2019-07-15 | 2 | -0/+30 |
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* | vhdl: avoid a crash on no matching operator error. | Tristan Gingold | 2019-07-15 | 1 | -1/+7 |
| | | | | Fix #869 | ||||
* | vhdl-sem_names: avoid a crash on parenthesis of | Tristan Gingold | 2019-07-15 | 1 | -2/+2 |
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* | find_top_entity: avoid crash on missing entity, handle | Tristan Gingold | 2019-07-15 | 2 | -13/+27 |
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* | synth: handle instantiation within generate statement. | Tristan Gingold | 2019-07-15 | 1 | -0/+2 |
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* | ghdlsynth: quit early in case of error. | Tristan Gingold | 2019-07-15 | 1 | -1/+10 |
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* | synth: handle choices by range in aggregates. | Tristan Gingold | 2019-07-15 | 3 | -12/+33 |
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* | synth: handle anonymous subtypes in array subtypes. | Tristan Gingold | 2019-07-15 | 1 | -4/+10 |
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* | synth: add comments. | Tristan Gingold | 2019-07-15 | 1 | -6/+10 |
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* | synth: remove extra elaboration of port types. | Tristan Gingold | 2019-07-15 | 1 | -18/+2 |
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* | synth: apply block configuration to for-generate statements. | Tristan Gingold | 2019-07-15 | 1 | -2/+15 |
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* | synth: use correct instance to synth default expressions of assocs. | Tristan Gingold | 2019-07-15 | 1 | -10/+13 |
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* | synth: save and restore instance_pool for processes. | Tristan Gingold | 2019-07-15 | 1 | -2/+4 |
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* | synth: improve support of components (anon subtypes). | Tristan Gingold | 2019-07-14 | 1 | -0/+15 |
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* | ghdlsynth: check top entity can be a top entity. | Tristan Gingold | 2019-07-14 | 5 | -23/+41 |
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* | vhdl: refactoring: remove configure function with string access. | Tristan Gingold | 2019-07-14 | 8 | -105/+95 |
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* | vhdl: set location on reference to the anonymous signal declaration. | Tristan Gingold | 2019-07-14 | 1 | -0/+1 |
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* | ghdlsynth: automatically find top entity if not specified. | Tristan Gingold | 2019-07-14 | 1 | -8/+33 |
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* | vhdl: fixes in find_top_entity (handle for-generate, remove early return) | Tristan Gingold | 2019-07-14 | 2 | -5/+27 |
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* | synth: handle anonymous signals. | Tristan Gingold | 2019-07-14 | 1 | -0/+3 |
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* | Add a test for previous commit. | Tristan Gingold | 2019-07-13 | 1 | -0/+3 |
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* | synth: handle black boxes. | Tristan Gingold | 2019-07-13 | 3 | -47/+108 |
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* | Add a test for component instances. | Tristan Gingold | 2019-07-13 | 2 | -3/+14 |
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* | synth: handle simple component instances. | Tristan Gingold | 2019-07-13 | 1 | -36/+256 |
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* | vhdl: cleanup in clear_instantiation_configuration. | Tristan Gingold | 2019-07-13 | 4 | -70/+23 |
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* | simul-elaboration: rewrite assertion. | Tristan Gingold | 2019-07-13 | 1 | -3/+3 |
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* | add TCE to ->Who uses GHDL (#868) | TopiLeppanen | 2019-07-12 | 2 | -2/+12 |
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* | vhdl-configuration: improve error message. | Tristan Gingold | 2019-07-11 | 1 | -1/+1 |
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* | vhdl: minor reformating. | Tristan Gingold | 2019-07-11 | 2 | -8/+5 |
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* | synth: set flag_elaborate. | Tristan Gingold | 2019-07-11 | 2 | -1/+3 |
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* | vhdl-sem_lib: save and restore nbr_errors in | Tristan Gingold | 2019-07-11 | 1 | -0/+10 |
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* | libghdl: import Free_Dependence_List. | Tristan Gingold | 2019-07-11 | 3 | -0/+6 |
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* | vhdl-nodes: add comments | Tristan Gingold | 2019-07-11 | 1 | -0/+16 |
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* | synth_top_entity: pass config + minor cleanup. | Tristan Gingold | 2019-07-11 | 3 | -13/+7 |
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* | synth-insts: minor cleanup. | Tristan Gingold | 2019-07-11 | 1 | -7/+0 |
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* | synth: do not crash on use of std_logic_1164 2008. | Tristan Gingold | 2019-07-10 | 2 | -12/+10 |
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* | synth: add synth_top_entity. | Tristan Gingold | 2019-07-10 | 3 | -221/+96 |
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* | synth: add a simple test for instantiation. | Tristan Gingold | 2019-07-10 | 5 | -0/+105 |
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* | synth: add Id_Port gate to improve display. | Tristan Gingold | 2019-07-10 | 5 | -29/+73 |
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* | synth: display instances in reverse order. | Tristan Gingold | 2019-07-10 | 2 | -10/+41 |
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* | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 11 | -48/+587 |
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* | vhdl: improve an error message. | Tristan Gingold | 2019-07-10 | 1 | -1/+1 |
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* | Add synth testsuite to CI (#862) | 1138-4EB | 2019-07-10 | 5 | -34/+71 |
| | | | | | | | | | | | | * add synth testsuite to CI * update travis jobs to fedora29 * travis: add 'dummy' image name to man job * travis: update Debian from Stretch to Buster * update travis jobs to fedora30 |