Add a test for component instances.

2 files changed, 14 insertions, 3 deletions

diff --git a/testsuite/synth/comp01/and6comp.vhdl b/testsuite/synth/comp01/and6comp.vhdl
index 8cdb8f821..366992449 100644
--- a/testsuite/synth/comp01/and6comp.vhdl
+++ b/testsuite/synth/comp01/and6comp.vhdl
@@ -1,12 +1,12 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity and6comp is
+entity and6 is
   port (i0, i1, i2, i3, i4, i5 : std_logic;
         o : out std_logic);
-end and6comp;
+end and6;
 
-architecture behav of and6comp is
+architecture behav of and6 is
   component and3 is
     port (a, b, c : std_logic;
           o : out std_logic);
diff --git a/testsuite/synth/comp01/testsuite.sh b/testsuite/synth/comp01/testsuite.sh
index c16175e4c..108959752 100755
--- a/testsuite/synth/comp01/testsuite.sh
+++ b/testsuite/synth/comp01/testsuite.sh
@@ -6,6 +6,7 @@
 
 . ../../testenv.sh
 
+# Direct instance
 analyze and3.vhdl and6.vhdl tb_and6.vhdl
 elab_simulate tb_and6
 clean
@@ -15,4 +16,14 @@ analyze syn_and6.vhdl tb_and6.vhdl
 elab_simulate tb_and6
 clean
 
+# Component instance
+analyze and3.vhdl and6comp.vhdl tb_and6.vhdl
+elab_simulate tb_and6
+clean
+
+synth and3.vhdl and6comp.vhdl -e and6 > syn_and6.vhdl
+analyze syn_and6.vhdl tb_and6.vhdl
+elab_simulate tb_and6
+clean
+
 echo "Test successful"