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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-11 06:56:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-11 06:56:03 +0200 |
| commit | bb882cc4d904f99656f7168041ed0f9137f7b14d (patch) | |
| tree | bdb76d87a7f5217e5c34ce089fb30a16b6d5484a | |
| parent | e24abb5093365dfc578a154d9b89d84ca145a4fe (diff) | |
| download | ghdl-bb882cc4d904f99656f7168041ed0f9137f7b14d.tar.gz ghdl-bb882cc4d904f99656f7168041ed0f9137f7b14d.tar.bz2 ghdl-bb882cc4d904f99656f7168041ed0f9137f7b14d.zip | |
synth-insts: minor cleanup.
| -rw-r--r-- | src/synth/synth-insts.adb | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 3201f7254..c9d3a5b33 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -240,7 +240,6 @@ package body Synth.Insts is Inter : Node; Nbr_Inputs : Port_Nbr; Nbr_Outputs : Port_Nbr; - Num : Uns32; Inst_Obj : Inst_Object; Inst : Instance; begin @@ -275,8 +274,6 @@ package body Synth.Insts is -- FIXME: what about unconstrained ports ? Get the type from the -- association. Inter := Get_Port_Chain (Ent); - Nbr_Inputs := 0; - Nbr_Outputs := 0; while Is_Valid (Inter) loop if not Is_Fully_Constrained_Type (Get_Type (Inter)) then -- TODO @@ -286,13 +283,9 @@ package body Synth.Insts is case Mode_To_Port_Kind (Get_Mode (Inter)) is when Port_In => Make_Object (Sub_Inst, Wire_None, Inter); - Num := Get_Nbr_Wire (Get_Value (Sub_Inst, Inter)); - Nbr_Inputs := Nbr_Inputs + Port_Nbr (Num); when Port_Out | Port_Inout => Make_Object (Sub_Inst, Wire_None, Inter); - Num := Get_Nbr_Wire (Get_Value (Sub_Inst, Inter)); - Nbr_Outputs := Nbr_Outputs + Port_Nbr (Num); end case; Inter := Get_Chain (Inter); end loop; |