vhdl: fixes in find_top_entity (handle for-generate, remove early return)

2 files changed, 27 insertions, 5 deletions

diff --git a/src/vhdl/vhdl-configuration.adb b/src/vhdl/vhdl-configuration.adb
index 42db12342..c3d2db613 100644
--- a/src/vhdl/vhdl-configuration.adb
+++ b/src/vhdl/vhdl-configuration.adb
@@ -792,12 +792,16 @@ package body Vhdl.Configuration is
    package body Top is
       use Nodes_Walk;
 
+      --  Add entities to the name table (so that they easily could be found).
       function Add_Entity_Cb (Design : Iir) return Walk_Status
       is
          Kind : constant Iir_Kind := Get_Kind (Get_Library_Unit (Design));
       begin
-         if Get_Date (Design) < Date_Analyzed then
-            return Walk_Continue;
+         if not Flags.Flag_Elaborate_With_Outdated then
+            --  Discard obsolete or non-analyzed units.
+            if Get_Date (Design) < Date_Analyzed then
+               return Walk_Continue;
+            end if;
          end if;
 
          case Iir_Kinds_Library_Unit (Kind) is
@@ -886,8 +890,10 @@ package body Vhdl.Configuration is
          Unit : constant Iir := Get_Library_Unit (Design);
          Status : Walk_Status;
       begin
-         if Get_Date (Design) < Date_Analyzed then
-            return Walk_Continue;
+         if not Flags.Flag_Elaborate_With_Outdated then
+            if Get_Date (Design) < Date_Analyzed then
+               return Walk_Continue;
+            end if;
          end if;
 
          case Iir_Kinds_Library_Unit (Get_Kind (Unit)) is
@@ -938,8 +944,13 @@ package body Vhdl.Configuration is
       begin
          if Get_Kind (Unit) = Iir_Kind_Entity_Declaration then
             if Get_Elab_Flag (Design) then
+               --  Clean elab flag.
                Set_Elab_Flag (Design, False);
             else
+               if Flags.Verbose then
+                  Report_Msg (Msgid_Note, Elaboration, +Unit,
+                              "candidate for top entity: %n", (1 => +Unit));
+               end if;
                Nbr_Top_Entities := Nbr_Top_Entities + 1;
                if Nbr_Top_Entities = 1 then
                   First_Top_Entity := Unit;
diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb
index 1f33ee23f..e9ae956a7 100644
--- a/src/vhdl/vhdl-nodes_walk.adb
+++ b/src/vhdl/vhdl-nodes_walk.adb
@@ -158,7 +158,10 @@ package body Vhdl.Nodes_Walk is
          case Iir_Kinds_Concurrent_Statement (Get_Kind (El)) is
             when Iir_Kinds_Simple_Concurrent_Statement
               | Iir_Kind_Component_Instantiation_Statement =>
-               return Cb.all (El);
+               Status := Cb.all (El);
+               if Status /= Walk_Continue then
+                  return Status;
+               end if;
             when Iir_Kind_Block_Statement =>
                Status := Cb.all (El);
                if Status /= Walk_Continue then
@@ -166,6 +169,14 @@ package body Vhdl.Nodes_Walk is
                end if;
                return Walk_Concurrent_Statements_Chain
                  (Get_Concurrent_Statement_Chain (El), Cb);
+            when Iir_Kind_For_Generate_Statement =>
+               Status := Cb.all (El);
+               if Status /= Walk_Continue then
+                  return Status;
+               end if;
+               return Walk_Concurrent_Statements_Chain
+                 (Get_Concurrent_Statement_Chain
+                    (Get_Generate_Statement_Body (El)), Cb);
             when others =>
                Error_Kind ("walk_concurrent_statements_chain", El);
          end case;