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* netlists-builders: allow building mem_wr_sync without clk and en.Tristan Gingold2022-11-051-4/+10
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* synth: infere a dff (instead of an idff) when the init value is XTristan Gingold2022-11-032-6/+21
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* testsuite/synth/issue2035: avoid warningsTristan Gingold2022-11-021-0/+2
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* testsuite/gna: add a test for #2238Tristan Gingold2022-11-022-0/+27
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* vhdl-sem_expr(sem_qualified_expression): relax staticness rules.Tristan Gingold2022-11-021-1/+11
| | | | Fix #2238
* testsuite/synth: add tests for #2237Tristan Gingold2022-11-029-0/+746
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* synth: handle bit/unsigned and bit/signed vhdl 08 operators.Tristan Gingold2022-11-021-12/+36
| | | | Fix #2237
* Add missing -g for generic override to CLI help for RUNOPTS (#2220)svnesbo2022-11-011-0/+1
| | | Co-authored-by: Simon Voigt Nesbo <Simon.Voigt.Nesbo@hvl.no>
* testsuite/synth: add a test for #2231Tristan Gingold2022-10-303-0/+90
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* netlists-inference: handle flip-flop with different patterns.Tristan Gingold2022-10-301-23/+75
| | | | Fix #2231
* netlists-gates: add a commentTristan Gingold2022-10-301-0/+1
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* testsuite/gna: add tests for #2233Tristan Gingold2022-10-295-0/+137
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* vhdl-sem_names(sem_name_free): handle iir_kind_slice_name. For #2233Tristan Gingold2022-10-291-0/+1
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* vhdl-evaluation: handle to_string_digits. For #2233Tristan Gingold2022-10-291-5/+50
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* synth: internal refactoringTristan Gingold2022-10-294-121/+93
| | | | use memtyp for eval_static_predefined_function_call
* elab-vhdl_types: abstract elab_floating_type_definitionTristan Gingold2022-10-291-10/+15
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* testsuite/synth: add a test for #2234Tristan Gingold2022-10-294-0/+775
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* synth: fix crash in disp_verilog. Fix #2234Tristan Gingold2022-10-291-3/+8
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* synth: handle copyback associations in any order.Tristan Gingold2022-10-191-12/+30
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* synth-vhdl_eval: handle std_logic_misc reduce functionsTristan Gingold2022-10-191-0/+27
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* testsuite/synth: add tests for std_logic_misc reduce functionsTristan Gingold2022-10-194-16/+90
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* synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_miscTristan Gingold2022-10-191-16/+34
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* testsuite/synth: add a test for #2224Tristan Gingold2022-10-192-0/+23
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* synth-vhdl_oper: handle and_reduce. Fix #2224Tristan Gingold2022-10-191-1/+10
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* testsuite/synth: add a test for #2222Tristan Gingold2022-10-182-0/+28
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* synth: extract elab-vhdl_utils from synth-vhdl_stmts.Tristan Gingold2022-10-183-142/+241
| | | | Fix #2222
* testsuite/gna: add test for #2221Tristan Gingold2022-10-182-0/+42
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* vhdl-sem_assocs: handle association with external signal names.Tristan Gingold2022-10-184-63/+77
| | | | Fix #2221
* gha: disable macosx-12 buildTristan Gingold2022-10-171-1/+1
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* workflows: adjust macosx deployment targetTristan Gingold2022-10-171-1/+1
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* win64: fix FP argument passingTristan Gingold2022-10-171-2/+8
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* testsuite/gna: add a test for #2215Tristan Gingold2022-10-173-0/+55
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* github action: set macosx deployment env variableTristan Gingold2022-10-171-0/+1
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* testsuite/gna: add a test for #2218Tristan Gingold2022-10-163-0/+58
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* vhdl-sem_expr.adb: avoid crash after error on aggregate. Fix #2218Tristan Gingold2022-10-161-0/+6
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* testsuite/gna: add a test for #2217Tristan Gingold2022-10-164-0/+79
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* vhdl-sem_expr.adb(is_string_type): check character type.Tristan Gingold2022-10-161-1/+3
| | | | Fix #2217
* testsuite/gna: add a test for #2219Tristan Gingold2022-10-142-0/+39
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* vhdl-parse.adb: handle external names as assignment target.Tristan Gingold2022-10-141-2/+4
| | | | Fix #2219
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
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* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
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* synth: avoid extra conversion during alias elaborationTristan Gingold2022-10-141-6/+4
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* simul: fix spurious error about multiple driversTristan Gingold2022-10-141-0/+2
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* simul: handle delayed attributeTristan Gingold2022-10-142-6/+66
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* synth: handle alias of access objects.Tristan Gingold2022-10-131-1/+1
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* simul: handle last_event and last_activeTristan Gingold2022-10-133-4/+114
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* elab-vhd_expr: handle more cases in exec_type_of_objectTristan Gingold2022-10-131-1/+4
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* simul-vhdl_simul: keep default value of collapsed signalsTristan Gingold2022-10-131-1/+10
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* simul-vhdl_elab: fix crash on association with implicit signalsTristan Gingold2022-10-131-1/+4
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* simul: fix a crash due to missing strideTristan Gingold2022-10-131-5/+7
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