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author | Tristan Gingold <tgingold@free.fr> | 2022-10-19 05:25:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-10-19 05:25:05 +0200 |
commit | 375491d074dd9f270b5890c8dc0740c47d9efa37 (patch) | |
tree | 36f224e67c8cbe1fa1a05c38c5d394321a00217f | |
parent | 693466dceafbbca9cf060e4ee8e43b8abf1173cd (diff) | |
download | ghdl-375491d074dd9f270b5890c8dc0740c47d9efa37.tar.gz ghdl-375491d074dd9f270b5890c8dc0740c47d9efa37.tar.bz2 ghdl-375491d074dd9f270b5890c8dc0740c47d9efa37.zip |
testsuite/synth: add a test for #2224
-rw-r--r-- | testsuite/synth/issue2224/test.vhdl | 16 | ||||
-rwxr-xr-x | testsuite/synth/issue2224/testsuite.sh | 7 |
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue2224/test.vhdl b/testsuite/synth/issue2224/test.vhdl new file mode 100644 index 000000000..14d96cc3f --- /dev/null +++ b/testsuite/synth/issue2224/test.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; + +entity test is +port ( + clk : in std_logic; + d : in std_logic_vector(2 downto 0); + q : out std_logic +); +end entity; + +architecture rtl of test is +begin + q <= and_reduce(d); +end architecture; diff --git a/testsuite/synth/issue2224/testsuite.sh b/testsuite/synth/issue2224/testsuite.sh new file mode 100755 index 000000000..ea723b22a --- /dev/null +++ b/testsuite/synth/issue2224/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only test + +echo "Test successful" |