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author | Tristan Gingold <tgingold@free.fr> | 2022-11-02 18:45:48 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-02 20:58:23 +0100 |
commit | 63de2c1cca707bedc536815b991e177d4ab6e022 (patch) | |
tree | ec9285c7885acd052d4e7a95dcb45be8d2ed4abb | |
parent | 25fe65a7dd9172d4368ead88393c43c3f2329fdf (diff) | |
download | ghdl-63de2c1cca707bedc536815b991e177d4ab6e022.tar.gz ghdl-63de2c1cca707bedc536815b991e177d4ab6e022.tar.bz2 ghdl-63de2c1cca707bedc536815b991e177d4ab6e022.zip |
testsuite/synth/issue2035: avoid warnings
-rw-r--r-- | testsuite/synth/issue2035/cdc_fifo_rtl.vhdl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl b/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl index 059804d69..f5dea887a 100644 --- a/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl +++ b/testsuite/synth/issue2035/cdc_fifo_rtl.vhdl @@ -10,4 +10,6 @@ ARCHITECTURE rtl OF cdc_fifo IS ATTRIBUTE gclk : boolean; ATTRIBUTE gclk OF ver_clk : SIGNAL is true; BEGIN + ver_clk <= '0'; + assert ver_clk = '0'; END ARCHITECTURE; |