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author | Tristan Gingold <tgingold@free.fr> | 2022-10-30 17:51:10 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-10-30 17:51:10 +0100 |
commit | 1cc85c5788f3181081ab92aefc913787a51e48e7 (patch) | |
tree | 42cc29f8061f55e67dee704077b53e2f07169bc6 | |
parent | 2a05b90eb163a582fce9f9dd91ef07d0d77fb47c (diff) | |
download | ghdl-1cc85c5788f3181081ab92aefc913787a51e48e7.tar.gz ghdl-1cc85c5788f3181081ab92aefc913787a51e48e7.tar.bz2 ghdl-1cc85c5788f3181081ab92aefc913787a51e48e7.zip |
testsuite/synth: add a test for #2231
-rw-r--r-- | testsuite/synth/issue2231/areset.vhdl | 28 | ||||
-rw-r--r-- | testsuite/synth/issue2231/tb_areset.vhdl | 55 | ||||
-rwxr-xr-x | testsuite/synth/issue2231/testsuite.sh | 7 |
3 files changed, 90 insertions, 0 deletions
diff --git a/testsuite/synth/issue2231/areset.vhdl b/testsuite/synth/issue2231/areset.vhdl new file mode 100644 index 000000000..fb20e2a31 --- /dev/null +++ b/testsuite/synth/issue2231/areset.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity areset is + port ( + clk_sys : in std_logic; + reset_n : in std_logic; + d : in std_logic; + q : out std_logic_vector(1 downto 0) + ); +end entity; + +architecture rtl of areset is + signal q_i : std_logic_vector(1 downto 0); +begin + + process(clk_sys,reset_n) begin + if reset_n='0' then + q_i(0)<='0'; + elsif rising_edge(clk_sys) then + q_i(1)<=d; + q_i(0)<='1'; + end if; + end process; + + q<=q_i; + +end architecture; diff --git a/testsuite/synth/issue2231/tb_areset.vhdl b/testsuite/synth/issue2231/tb_areset.vhdl new file mode 100644 index 000000000..55b56c680 --- /dev/null +++ b/testsuite/synth/issue2231/tb_areset.vhdl @@ -0,0 +1,55 @@ +entity tb_areset is +end tb_areset; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_areset is + signal clk : std_logic; + signal rst_n : std_logic; + signal din : std_logic; + signal dout : std_logic_vector(1 downto 0); +begin + dut: entity work.areset + port map ( + clk_sys => clk, + reset_n => rst_n, + d => din, + q => dout); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + din <= '0'; + rst_n <= '0'; + pulse; + assert dout (0) = '0' severity failure; + + din <= '1'; + pulse; + assert dout (0) = '0' severity failure; + + rst_n <= '1'; + pulse; + assert dout (0) = '1' severity failure; + assert dout (1) = '1' severity failure; + + din <= '0'; + pulse; + assert dout (0) = '1' severity failure; + assert dout (1) = '0' severity failure; + + din <= '1'; + rst_n <= '0'; + pulse; + assert dout (0) = '0' severity failure; + assert dout (1) = '0' severity failure; +wait; + end process; +end behav; diff --git a/testsuite/synth/issue2231/testsuite.sh b/testsuite/synth/issue2231/testsuite.sh new file mode 100755 index 000000000..b98df94ee --- /dev/null +++ b/testsuite/synth/issue2231/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_tb areset + +echo "Test successful" |