testsuite/gna: add a test for #2218

3 files changed, 58 insertions, 0 deletions

diff --git a/testsuite/gna/issue2218/test.vhdl b/testsuite/gna/issue2218/test.vhdl
new file mode 100644
index 000000000..8b5d059cb
--- /dev/null
+++ b/testsuite/gna/issue2218/test.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+architecture beh of test is
+  type t_unsigned_vector is array (natural range <>) of unsigned;
+  type t_range_uns_vec is array (natural range <>) of t_unsigned_vector;
+  procedure ptest(
+    constant range_vec : in t_range_uns_vec) is
+  begin
+  end procedure;
+begin
+process(all)
+  variable v_sig_long_min : unsigned(127 downto 0) := x"8F000000000000000000000000000000";
+  variable v_sig_long_max : unsigned(127 downto 0) := x"8F000000000000000000000000000008";
+  variable v_slv_long_min  : std_logic_vector(127 downto 0) := x"8F000000000000000000000000000000";
+  variable v_slv_long_max  : std_logic_vector(127 downto 0) := x"8F000000000000000000000000000008";
+begin
+  ptest((0 => (v_sig_long_min, v_sig_long_max)));
+  ptest((0 => (unsigned(v_slv_long_min), unsigned(v_slv_long_max))));
+end process;
+end architecture beh;
diff --git a/testsuite/gna/issue2218/test2.vhdl b/testsuite/gna/issue2218/test2.vhdl
new file mode 100644
index 000000000..7cdf166c1
--- /dev/null
+++ b/testsuite/gna/issue2218/test2.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+architecture beh of test is
+  -- type t_unsigned_vector is array (natural range <>) of unsigned;
+  type t_range_uns_vec is array (natural range <>) of t_unsigned_vector;
+  procedure ptest(
+    constant range_vec : in t_range_uns_vec) is
+  begin
+  end procedure;
+begin
+process(all)
+  variable v_sig_long_min : unsigned(127 downto 0) := x"8F000000000000000000000000000000";
+  variable v_sig_long_max : unsigned(127 downto 0) := x"8F000000000000000000000000000008";
+  variable v_slv_long_min  : std_logic_vector(127 downto 0) := x"8F000000000000000000000000000000";
+  variable v_slv_long_max  : std_logic_vector(127 downto 0) := x"8F000000000000000000000000000008";
+begin
+  ptest((0 => (v_sig_long_min, v_sig_long_max)));
+  ptest((0 => (unsigned(v_slv_long_min), unsigned(v_slv_long_max))));
+end process;
+end architecture beh;
diff --git a/testsuite/gna/issue2218/testsuite.sh b/testsuite/gna/issue2218/testsuite.sh
new file mode 100755
index 000000000..3d1ceb7da
--- /dev/null
+++ b/testsuite/gna/issue2218/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze_failure test2.vhdl
+
+clean
+
+echo "Test successful"