diff options
Diffstat (limited to 'testsuite/synth/issue2013')
-rw-r--r-- | testsuite/synth/issue2013/tb_tc2.vhdl | 34 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tb_tc3.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tb_tc4.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tb_testcase.vhdl | 34 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tc2.vhdl | 30 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tc3.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/issue2013/tc4.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/issue2013/testcase.vhdl | 32 | ||||
-rwxr-xr-x | testsuite/synth/issue2013/testsuite.sh | 10 |
9 files changed, 238 insertions, 0 deletions
diff --git a/testsuite/synth/issue2013/tb_tc2.vhdl b/testsuite/synth/issue2013/tb_tc2.vhdl new file mode 100644 index 000000000..8c58b2054 --- /dev/null +++ b/testsuite/synth/issue2013/tb_tc2.vhdl @@ -0,0 +1,34 @@ +entity tb_tc2 is +end tb_tc2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_tc2 is + signal state : std_ulogic; + signal class : std_ulogic; + signal o : std_ulogic_vector(3 downto 0); +begin + dut: entity work.tc2 + port map (state, class, o); + + process + begin + state <= '0'; + class <= '0'; + wait for 1 ns; + assert o = "0111"; + + state <= '1'; + class <= '0'; + wait for 1 ns; + assert o = "1000"; + + state <= '1'; + class <= '1'; + wait for 1 ns; + assert o = "1000"; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2013/tb_tc3.vhdl b/testsuite/synth/issue2013/tb_tc3.vhdl new file mode 100644 index 000000000..35579b791 --- /dev/null +++ b/testsuite/synth/issue2013/tb_tc3.vhdl @@ -0,0 +1,26 @@ +entity tb_tc3 is +end tb_tc3; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_tc3 is + signal state : std_ulogic; + signal o : std_ulogic_vector(3 downto 0); +begin + dut: entity work.tc3 + port map (state, o); + + process + begin + state <= '0'; + wait for 1 ns; + assert o = "0111" severity failure; + + state <= '1'; + wait for 1 ns; + assert o = "1000" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2013/tb_tc4.vhdl b/testsuite/synth/issue2013/tb_tc4.vhdl new file mode 100644 index 000000000..188651670 --- /dev/null +++ b/testsuite/synth/issue2013/tb_tc4.vhdl @@ -0,0 +1,23 @@ +entity tb_tc4 is +end tb_tc4; + +architecture behav of tb_tc4 is + signal state : bit; + signal o : bit_vector(3 downto 0); +begin + dut: entity work.tc4 + port map (state, o); + + process + begin + state <= '0'; + wait for 1 ns; + assert o = "0111" severity failure; + + state <= '1'; + wait for 1 ns; + assert o = "1000" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2013/tb_testcase.vhdl b/testsuite/synth/issue2013/tb_testcase.vhdl new file mode 100644 index 000000000..84fbd7c14 --- /dev/null +++ b/testsuite/synth/issue2013/tb_testcase.vhdl @@ -0,0 +1,34 @@ +entity tb_testcase is +end tb_testcase; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_testcase is + signal state : std_ulogic; + signal class : std_ulogic; + signal o : std_ulogic_vector(3 downto 0); +begin + dut: entity work.testcase + port map (state, class, o); + + process + begin + state <= '0'; + class <= '0'; + wait for 1 ns; + assert o = "0111"; + + state <= '1'; + class <= '0'; + wait for 1 ns; + assert o = "0000"; + + state <= '1'; + class <= '1'; + wait for 1 ns; + assert o = "1000"; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2013/tc2.vhdl b/testsuite/synth/issue2013/tc2.vhdl new file mode 100644 index 000000000..0c90c101a --- /dev/null +++ b/testsuite/synth/issue2013/tc2.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tc2 is + port ( + state : in std_ulogic; + class : in std_ulogic; + o : out std_ulogic_vector(3 downto 0) + ); +end entity tc2; + +architecture behaviour of tc2 is + signal misc_sel : std_ulogic_vector(3 downto 0); +begin + testcase_0: process(all) + begin + misc_sel <= "0000"; + + case state is + when '0' => + misc_sel <= "0111"; + when '1' => + misc_sel(3) <= '1'; + when others => + end case; + + o <= misc_sel; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue2013/tc3.vhdl b/testsuite/synth/issue2013/tc3.vhdl new file mode 100644 index 000000000..da029fe9a --- /dev/null +++ b/testsuite/synth/issue2013/tc3.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tc3 is + port ( + state : in std_ulogic; + o : out std_ulogic_vector(3 downto 0) + ); +end entity tc3; + +architecture behaviour of tc3 is + signal misc_sel : std_ulogic_vector(3 downto 0); +begin + testcase_0: process(all) + begin + misc_sel <= "0000"; + + if state = '0' then + misc_sel <= "0111"; + else + misc_sel(3) <= '1'; + end if; + + o <= misc_sel; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue2013/tc4.vhdl b/testsuite/synth/issue2013/tc4.vhdl new file mode 100644 index 000000000..143a893fe --- /dev/null +++ b/testsuite/synth/issue2013/tc4.vhdl @@ -0,0 +1,23 @@ +entity tc4 is + port ( + state : in bit; + o : out bit_vector(3 downto 0) + ); +end entity tc4; + +architecture behaviour of tc4 is + signal misc_sel : bit_vector(3 downto 0); +begin + testcase_0: process(all) + begin + misc_sel <= "0000"; + + if state = '0' then + misc_sel <= "0111"; + else + misc_sel(3) <= '1'; + end if; + + o <= misc_sel; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue2013/testcase.vhdl b/testsuite/synth/issue2013/testcase.vhdl new file mode 100644 index 000000000..a5bfa1bff --- /dev/null +++ b/testsuite/synth/issue2013/testcase.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testcase is + port ( + state : in std_ulogic; + class : in std_ulogic; + o : out std_ulogic_vector(3 downto 0) + ); +end entity testcase; + +architecture behaviour of testcase is + signal misc_sel : std_ulogic_vector(3 downto 0); +begin + testcase_0: process(all) + begin + misc_sel <= "0000"; + + case state is + when '0' => + misc_sel <= "0111"; + when '1' => + if class = '1' then + misc_sel(3) <= '1'; + end if; + when others => + end case; + + o <= misc_sel; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue2013/testsuite.sh b/testsuite/synth/issue2013/testsuite.sh new file mode 100755 index 000000000..a96ccc5dd --- /dev/null +++ b/testsuite/synth/issue2013/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +for t in testcase tc3 tc2 tc4; do + synth_tb $t +done + +echo "Test successful" |