testsuite/synth/issue2013/tc2.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tc2 is
    port (
        state   : in std_ulogic;
        class   : in std_ulogic;
        o       : out std_ulogic_vector(3 downto 0)
        );
end entity tc2;

architecture behaviour of tc2 is
    signal misc_sel      : std_ulogic_vector(3 downto 0);
begin
    testcase_0: process(all)
    begin
        misc_sel <= "0000";

        case state is
           when '0' =>
                misc_sel <= "0111";
           when '1' =>
             misc_sel(3) <= '1';
           when others =>
        end case;

        o <= misc_sel;
    end process;
end architecture behaviour;