diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
| commit | 8ca210a4af9fd039e290cfcc309adde543999c1f (patch) | |
| tree | 1aa594d5e65d5ebabdd358acbe8d3a9ac29f2070 /os/hal/platforms/SPC5xx | |
| parent | cb453a3a12464dd71856b1354d083b5b02260870 (diff) | |
| download | ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.gz ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.bz2 ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx')
37 files changed, 0 insertions, 23445 deletions
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h deleted file mode 100644 index 4c6105e15..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h +++ /dev/null @@ -1,448 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DSPI_v1/spc5_dspi.h
- * @brief SPC5xx DSPI header file.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPC5_DSPI_H_
-#define _SPC5_DSPI_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name MCR register definitions
- * @{
- */
-#define SPC5_MCR_MSTR (1U << 31)
-#define SPC5_MCR_CONT_SCKE (1U << 30)
-#define SPC5_MCR_DCONF_MASK (3U << 28)
-#define SPC5_MCR_FRZ (1U << 27)
-#define SPC5_MCR_MTFE (1U << 26)
-#define SPC5_MCR_PCSSE (1U << 25)
-#define SPC5_MCR_ROOE (1U << 24)
-#define SPC5_MCR_PCSIS7 (1U << 23)
-#define SPC5_MCR_PCSIS6 (1U << 22)
-#define SPC5_MCR_PCSIS5 (1U << 21)
-#define SPC5_MCR_PCSIS4 (1U << 20)
-#define SPC5_MCR_PCSIS3 (1U << 19)
-#define SPC5_MCR_PCSIS2 (1U << 18)
-#define SPC5_MCR_PCSIS1 (1U << 17)
-#define SPC5_MCR_PCSIS0 (1U << 16)
-#define SPC5_MCR_DOZE (1U << 15)
-#define SPC5_MCR_MDIS (1U << 14)
-#define SPC5_MCR_DIS_TXF (1U << 13)
-#define SPC5_MCR_DIS_RXF (1U << 12)
-#define SPC5_MCR_CLR_TXF (1U << 11)
-#define SPC5_MCR_CLR_RXF (1U << 10)
-#define SPC5_MCR_SMPL_PT_MASK (3U << 8)
-#define SPC5_MCR_SMPL_PT(n) ((n) << 8)
-#define SPC5_MCR_FCPCS (1U << 2)
-#define SPC5_MCR_PES (1U << 1)
-#define SPC5_MCR_HALT (1U << 0)
-/** @} */
-
-/**
- * @name RSER register definitions
- * @{
- */
-#define SPC5_RSER_TCF_RE (1U << 31)
-#define SPC5_RSER_DSITCF_RE (1U << 29)
-#define SPC5_RSER_EOQF_RE (1U << 28)
-#define SPC5_RSER_TFUF_RE (1U << 27)
-#define SPC5_RSER_SPITCF_RE (1U << 26)
-#define SPC5_RSER_TFFF_RE (1U << 25)
-#define SPC5_RSER_TFFF_DIRS (1U << 24)
-#define SPC5_RSER_DPEF_RE (1U << 22)
-#define SPC5_RSER_SPEF_RE (1U << 21)
-#define SPC5_RSER_DDIF_RE (1U << 20)
-#define SPC5_RSER_RFOF_RE (1U << 19)
-#define SPC5_RSER_RFDF_RE (1U << 17)
-#define SPC5_RSER_RFDF_DIRS (1U << 16)
-/** @} */
-
-/**
- * @name CTAR registers definitions
- * @{
- */
-#define SPC5_CTAR_DBR (1U << 31)
-#define SPC5_CTAR_FMSZ_MASK (15U << 27)
-#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27)
-#define SPC5_CTAR_CPOL (1U << 26)
-#define SPC5_CTAR_CPHA (1U << 25)
-#define SPC5_CTAR_LSBFE (1U << 24)
-#define SPC5_CTAR_PCSSCK_MASK (3U << 22)
-#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22)
-#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22)
-#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22)
-#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22)
-#define SPC5_CTAR_PASC_MASK (3U << 20)
-#define SPC5_CTAR_PASC_PRE1 (0U << 20)
-#define SPC5_CTAR_PASC_PRE3 (1U << 20)
-#define SPC5_CTAR_PASC_PRE5 (2U << 20)
-#define SPC5_CTAR_PASC_PRE7 (3U << 20)
-#define SPC5_CTAR_PDT_MASK (3U << 18)
-#define SPC5_CTAR_PDT_PRE1 (0U << 18)
-#define SPC5_CTAR_PDT_PRE3 (1U << 18)
-#define SPC5_CTAR_PDT_PRE5 (2U << 18)
-#define SPC5_CTAR_PDT_PRE7 (3U << 18)
-#define SPC5_CTAR_PBR_MASK (3U << 16)
-#define SPC5_CTAR_PBR_PRE2 (0U << 16)
-#define SPC5_CTAR_PBR_PRE3 (1U << 16)
-#define SPC5_CTAR_PBR_PRE5 (2U << 16)
-#define SPC5_CTAR_PBR_PRE7 (3U << 16)
-#define SPC5_CTAR_CSSCK_MASK (15U << 12)
-#define SPC5_CTAR_CSSCK_DIV2 (0U << 12)
-#define SPC5_CTAR_CSSCK_DIV4 (1U << 12)
-#define SPC5_CTAR_CSSCK_DIV6 (2U << 12)
-#define SPC5_CTAR_CSSCK_DIV8 (3U << 12)
-#define SPC5_CTAR_CSSCK_DIV16 (4U << 12)
-#define SPC5_CTAR_CSSCK_DIV32 (5U << 12)
-#define SPC5_CTAR_CSSCK_DIV64 (6U << 12)
-#define SPC5_CTAR_CSSCK_DIV128 (7U << 12)
-#define SPC5_CTAR_CSSCK_DIV256 (8U << 12)
-#define SPC5_CTAR_CSSCK_DIV512 (9U << 12)
-#define SPC5_CTAR_CSSCK_DIV1024 (10U << 12)
-#define SPC5_CTAR_CSSCK_DIV2048 (11U << 12)
-#define SPC5_CTAR_CSSCK_DIV4096 (12U << 12)
-#define SPC5_CTAR_CSSCK_DIV8192 (13U << 12)
-#define SPC5_CTAR_CSSCK_DIV16384 (14U << 12)
-#define SPC5_CTAR_CSSCK_DIV32768 (15U << 12)
-#define SPC5_CTAR_ASC_MASK (15U << 8)
-#define SPC5_CTAR_ASC_DIV2 (0U << 8)
-#define SPC5_CTAR_ASC_DIV4 (1U << 8)
-#define SPC5_CTAR_ASC_DIV6 (2U << 8)
-#define SPC5_CTAR_ASC_DIV8 (3U << 8)
-#define SPC5_CTAR_ASC_DIV16 (4U << 8)
-#define SPC5_CTAR_ASC_DIV32 (5U << 8)
-#define SPC5_CTAR_ASC_DIV64 (6U << 8)
-#define SPC5_CTAR_ASC_DIV128 (7U << 8)
-#define SPC5_CTAR_ASC_DIV256 (8U << 8)
-#define SPC5_CTAR_ASC_DIV512 (9U << 8)
-#define SPC5_CTAR_ASC_DIV1024 (10U << 8)
-#define SPC5_CTAR_ASC_DIV2048 (11U << 8)
-#define SPC5_CTAR_ASC_DIV4096 (12U << 8)
-#define SPC5_CTAR_ASC_DIV8192 (13U << 8)
-#define SPC5_CTAR_ASC_DIV16384 (14U << 8)
-#define SPC5_CTAR_ASC_DIV32768 (15U << 8)
-#define SPC5_CTAR_DT_MASK (15U << 4)
-#define SPC5_CTAR_DT_DIV2 (0U << 4)
-#define SPC5_CTAR_DT_DIV4 (1U << 4)
-#define SPC5_CTAR_DT_DIV6 (2U << 4)
-#define SPC5_CTAR_DT_DIV8 (3U << 4)
-#define SPC5_CTAR_DT_DIV16 (4U << 4)
-#define SPC5_CTAR_DT_DIV32 (5U << 4)
-#define SPC5_CTAR_DT_DIV64 (6U << 4)
-#define SPC5_CTAR_DT_DIV128 (7U << 4)
-#define SPC5_CTAR_DT_DIV256 (8U << 4)
-#define SPC5_CTAR_DT_DIV512 (9U << 4)
-#define SPC5_CTAR_DT_DIV1024 (10U << 4)
-#define SPC5_CTAR_DT_DIV2048 (11U << 4)
-#define SPC5_CTAR_DT_DIV4096 (12U << 4)
-#define SPC5_CTAR_DT_DIV8192 (13U << 4)
-#define SPC5_CTAR_DT_DIV16384 (14U << 4)
-#define SPC5_CTAR_DT_DIV32768 (15U << 4)
-#define SPC5_CTAR_BR_MASK (15U << 0)
-#define SPC5_CTAR_BR_DIV2 (0U << 0)
-#define SPC5_CTAR_BR_DIV4 (1U << 0)
-#define SPC5_CTAR_BR_DIV6 (2U << 0)
-#define SPC5_CTAR_BR_DIV8 (3U << 0)
-#define SPC5_CTAR_BR_DIV16 (4U << 0)
-#define SPC5_CTAR_BR_DIV32 (5U << 0)
-#define SPC5_CTAR_BR_DIV64 (6U << 0)
-#define SPC5_CTAR_BR_DIV128 (7U << 0)
-#define SPC5_CTAR_BR_DIV256 (8U << 0)
-#define SPC5_CTAR_BR_DIV512 (9U << 0)
-#define SPC5_CTAR_BR_DIV1024 (10U << 0)
-#define SPC5_CTAR_BR_DIV2048 (11U << 0)
-#define SPC5_CTAR_BR_DIV4096 (12U << 0)
-#define SPC5_CTAR_BR_DIV8192 (13U << 0)
-#define SPC5_CTAR_BR_DIV16384 (14U << 0)
-#define SPC5_CTAR_BR_DIV32768 (15U << 0)
-/** @} */
-
-/**
- * @name PUSHR register definitions
- * @{
- */
-#define SPC5_PUSHR_CONT (1U << 31)
-#define SPC5_PUSHR_CTAS_MASK (3U << 28)
-#define SPC5_PUSHR_CTAS(n) ((n) << 29)
-#define SPC5_PUSHR_EOQ (1U << 27)
-#define SPC5_PUSHR_CTCNT (1U << 26)
-#define SPC5_PUSHR_MASC (1U << 25)
-#define SPC5_PUSHR_MCSC (1U << 24)
-#define SPC5_PUSHR_PCS_MASK (255U << 16)
-#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16)
-#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-struct spc5_dspi {
- union {
- vuint32_t R;
- struct {
- vuint32_t MSTR :1;
- vuint32_t CONT_SCKE :1;
- vuint32_t DCONF :2;
- vuint32_t FRZ :1;
- vuint32_t MTFE :1;
- vuint32_t PCSSE :1;
- vuint32_t ROOE :1;
- vuint32_t PCSIS7 :1;
- vuint32_t PCSIS6 :1;
- vuint32_t PCSIS5 :1;
- vuint32_t PCSIS4 :1;
- vuint32_t PCSIS3 :1;
- vuint32_t PCSIS2 :1;
- vuint32_t PCSIS1 :1;
- vuint32_t PCSIS0 :1;
- vuint32_t :1;
- vuint32_t MDIS :1;
- vuint32_t DIS_TXF :1;
- vuint32_t DIS_RXF :1;
- vuint32_t CLR_TXF :1;
- vuint32_t CLR_RXF :1;
- vuint32_t SMPL_PT :2;
- vuint32_t :7;
- vuint32_t HALT :1;
- } B;
- } MCR; /* Module Configuration Register */
-
- uint32_t dspi_reserved1;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCNT :16;
- vuint32_t :16;
- } B;
- } TCR;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t DBR :1;
- vuint32_t FMSZ :4;
- vuint32_t CPOL :1;
- vuint32_t CPHA :1;
- vuint32_t LSBFE :1;
- vuint32_t PCSSCK :2;
- vuint32_t PASC :2;
- vuint32_t PDT :2;
- vuint32_t PBR :2;
- vuint32_t CSSCK :4;
- vuint32_t ASC :4;
- vuint32_t DT :4;
- vuint32_t BR :4;
- } B;
- } CTAR[8]; /* Clock and Transfer Attributes Registers */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCF :1;
- vuint32_t TXRXS :1;
- vuint32_t :1;
- vuint32_t EOQF :1;
- vuint32_t TFUF :1;
- vuint32_t :1;
- vuint32_t TFFF :1;
- vuint32_t :5;
- vuint32_t RFOF :1;
- vuint32_t :1;
- vuint32_t RFDF :1;
- vuint32_t :1;
- vuint32_t TXCTR :4;
- vuint32_t TXNXTPTR :4;
- vuint32_t RXCTR :4;
- vuint32_t POPNXTPTR :4;
- } B;
- } SR; /* Status Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCFRE :1;
- vuint32_t :2;
- vuint32_t EOQFRE :1;
- vuint32_t TFUFRE :1;
- vuint32_t :1;
- vuint32_t TFFFRE :1;
- vuint32_t TFFFDIRS :1;
- vuint32_t :4;
- vuint32_t RFOFRE :1;
- vuint32_t :1;
- vuint32_t RFDFRE :1;
- vuint32_t RFDFDIRS :1;
- vuint32_t :16;
- } B;
- } RSER; /* DMA/Interrupt Request Select and Enable Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t CONT :1;
- vuint32_t CTAS :3;
- vuint32_t EOQ :1;
- vuint32_t CTCNT :1;
- vuint32_t :2;
- vuint32_t PCS7 :1;
- vuint32_t PCS6 :1;
- vuint32_t PCS5 :1;
- vuint32_t PCS4 :1;
- vuint32_t PCS3 :1;
- vuint32_t PCS2 :1;
- vuint32_t PCS1 :1;
- vuint32_t PCS0 :1;
- vuint32_t TXDATA :16;
- } B;
- } PUSHR; /* PUSH TX FIFO Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t RXDATA :16;
- } B;
- } POPR; /* POP RX FIFO Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TXCMD :16;
- vuint32_t TXDATA :16;
- } B;
- } TXFR[5]; /* Transmit FIFO Registers */
-
- vuint32_t DSPI_reserved_txf[11];
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t RXDATA :16;
- } B;
- } RXFR[5]; /* Receive FIFO Registers */
-
- vuint32_t DSPI_reserved_rxf[12];
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MTOE :1;
- vuint32_t :1;
- vuint32_t MTOCNT :6;
- vuint32_t :4;
- vuint32_t TXSS :1;
- vuint32_t TPOL :1;
- vuint32_t TRRE :1;
- vuint32_t CID :1;
- vuint32_t DCONT :1;
- vuint32_t DSICTAS :3;
- vuint32_t :6;
- vuint32_t DPCS5 :1;
- vuint32_t DPCS4 :1;
- vuint32_t DPCS3 :1;
- vuint32_t DPCS2 :1;
- vuint32_t DPCS1 :1;
- vuint32_t DPCS0 :1;
- } B;
- } DSICR; /* DSI Configuration Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t SER_DATA :16;
- } B;
- } SDR; /* DSI Serialization Data Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t ASER_DATA :16;
- } B;
- } ASDR; /* DSI Alternate Serialization Data Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t COMP_DATA :16;
- } B;
- } COMPR; /* DSI Transmit Comparison Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t DESER_DATA :16;
- } B;
- } DDR; /* DSI deserialization Data Register */
-
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name DSPI units references
- * @{
- */
-#if SPC5_HAS_DSPI0 || defined(__DOXYGEN__)
-#define SPC5_DSPI0 (*(struct spc5_dspi *)0xFFF90000U)
-#endif
-
-#if SPC5_HAS_DSPI1 || defined(__DOXYGEN__)
-#define SPC5_DSPI1 (*(struct spc5_dspi *)0xFFF94000U)
-#endif
-
-#if SPC5_HAS_DSPI2 || defined(__DOXYGEN__)
-#define SPC5_DSPI2 (*(struct spc5_dspi *)0xFFF98000U)
-#endif
-
-#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
-#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U)
-#endif
-
-#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
-#define SPC5_DSPI4 (*(struct spc5_dspi *)0x8FFA0000U)
-#endif
-/** @} */
-
-#endif /* _SPC5_DSPI_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c deleted file mode 100644 index f5db08a75..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c +++ /dev/null @@ -1,1218 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/DSPI_v1/spi_lld.c
- * @brief SPC5xx SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/* Some forward declarations.*/
-static void spi_serve_rx_irq(edma_channel_t channel, void *p);
-static void spi_serve_tx_irq(edma_channel_t channel, void *p);
-static void spi_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr);
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/* Excluded PUSHR bits.*/
-#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \
- SPC5_PUSHR_EOQ | \
- SPC5_PUSHR_TXDATA_MASK)
-
-#define DSPI_POPR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 3)
-#define DSPI_POPR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 2)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SPID1 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/**
- * @brief SPID2 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/**
- * @brief SPID3 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-SPIDriver SPID3;
-#endif
-
-/**
- * @brief SPID4 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-SPIDriver SPID4;
-#endif
-
-/**
- * @brief SPID5 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-SPIDriver SPID5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI0 TX1.
- */
-static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
- SPC5_DSPI0_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI0_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief DMA configuration for DSPI0 TX2.
- */
-static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
- SPC5_DSPI0_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief DMA configuration for DSPI0 RX.
- */
-static const edma_channel_config_t spi_dspi0_rx_dma_config = {
- SPC5_DSPI0_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI0_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1
-};
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI1 TX1.
- */
-static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
- SPC5_DSPI1_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI1_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief DMA configuration for DSPI1 TX2.
- */
-static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
- SPC5_DSPI1_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief DMA configuration for DSPI1 RX.
- */
-static const edma_channel_config_t spi_dspi1_rx_dma_config = {
- SPC5_DSPI1_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI1_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2
-};
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI2 TX1.
- */
-static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
- SPC5_DSPI2_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI2_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief DMA configuration for DSPI2 TX2.
- */
-static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
- SPC5_DSPI2_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief DMA configuration for DSPI2 RX.
- */
-static const edma_channel_config_t spi_dspi2_rx_dma_config = {
- SPC5_DSPI2_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI2_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3
-};
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI3 TX1.
- */
-static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
- SPC5_DSPI3_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI3_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief DMA configuration for DSPI3 TX2.
- */
-static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
- SPC5_DSPI3_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief DMA configuration for DSPI3 RX.
- */
-static const edma_channel_config_t spi_dspi3_rx_dma_config = {
- SPC5_DSPI3_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI3_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4
-};
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI4 TX1.
- */
-static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
- SPC5_DSPI4_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI4_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief DMA configuration for DSPI4 TX2.
- */
-static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
- SPC5_DSPI4_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief DMA configuration for DSPI4 RX.
- */
-static const edma_channel_config_t spi_dspi4_rx_dma_config = {
- SPC5_DSPI4_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI4_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5
-};
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Starts reception using DMA ignoring the received data.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_rx_ignore(SPIDriver *spip, size_t n) {
- static uint32_t datasink;
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR8_ADDRESS(spip), /* src. */
- &datasink, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 0, /* ssize, 16 bits transfers.*/
- 0, /* dsize, 16 bits transfers.*/
- 1, /* nbytes, always one. */
- n, /* iter. */
- 0, /* slast. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts reception using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx8(SPIDriver *spip,
- size_t n,
- uint8_t *rxbuf) {
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR8_ADDRESS(spip), /* src. */
- rxbuf, /* dst. */
- 0, /* soff, do not advance. */
- 1, /* doff, advance by one. */
- 0, /* ssize, 8 bits transfers. */
- 0, /* dsize, 8 bits transfers. */
- 1, /* nbytes, always one. */
- n, /* iter. */
- 0, /* slast. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts reception using DMA for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx16(SPIDriver *spip,
- size_t n,
- uint16_t *rxbuf) {
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR16_ADDRESS(spip), /* src. */
- rxbuf, /* dst. */
- 0, /* soff, do not advance. */
- 2, /* doff, advance by two. */
- 1, /* ssize, 16 bits transfers.*/
- 1, /* dsize, 16 bits transfers.*/
- 2, /* nbytes, always two. */
- n, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_tx_ignore(SPIDriver *spip, size_t n) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr | (uint32_t)0xFFFF;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_last = spip->tx_intbuf;
-
- /* Setting up TX1 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx1_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* Starting TX1 DMA channel.*/
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx8(SPIDriver *spip,
- size_t n,
- const uint8_t *txbuf) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
- /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
- edmaChannelSetupLinked(
- spip->tx1_channel, /* channel. */
- spip->tx2_channel, /* linkch. */
- txbuf + 1, /* src. */
- ((const uint8_t *)&spip->tx_intbuf) + 3, /* dst. */
- 1, /* soff, advance by 1. */
- 0, /* doff, do not advance. */
- 0, /* ssize, 8 bits transfers. */
- 0, /* dsize, 8 bits transfers. */
- 1, /* nbytes, always one. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ); /* mode. */
-
- /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx2_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* The last frame will be pushed by the TX DMA operation completion
- callback.*/
- spip->tx_last = txbuf[n - 1];
-
- /* Starting TX DMA channels.*/
- edmaChannelStart(spip->tx2_channel);
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx16(SPIDriver *spip,
- size_t n,
- const uint16_t *txbuf) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
- /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
- edmaChannelSetupLinked(
- spip->tx1_channel, /* channel. */
- spip->tx2_channel, /* linkch. */
- txbuf + 1, /* src. */
- ((const uint8_t *)&spip->tx_intbuf) + 2, /* dst. */
- 1, /* soff, advance by 1. */
- 0, /* doff, do not advance. */
- 1, /* ssize, 16 bits transfers.*/
- 1, /* dsize, 16 bits transfers.*/
- 1, /* nbytes, always one. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ); /* mode. */
-
- /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx2_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* The last frame will be pushed by the TX DMA operation completion
- callback.*/
- spip->tx_last = txbuf[n - 1];
-
- /* Starting TX DMA channels.*/
- edmaChannelStart(spip->tx2_channel);
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts idle bits using FIFO pre-filling.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_tx_prefill_ignore(SPIDriver *spip, size_t n) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)0xFFFF) &
- ~SPC5_PUSHR_CONT;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)0xFFFF;
- } while (TRUE);
-}
-
-/**
- * @brief Starts transmission using FIFO pre-filling for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill8(SPIDriver *spip,
- size_t n,
- const uint8_t *txbuf) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf) &
- ~SPC5_PUSHR_CONT;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
- txbuf++;
- } while (TRUE);
-}
-
-/**
- * @brief Starts transmission using FIFO pre-filling for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill16(SPIDriver *spip,
- size_t n,
- const uint16_t *txbuf) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
- txbuf++;
- } while (TRUE);
-}
-
-/**
- * @brief Shared RX DMA events service routine.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
- SPIDriver *spip = (SPIDriver *)p;
-
- /* Clearing RX channel state.*/
- edmaChannelStop(channel);
-
- /* Stops the DSPI and clears the queues.*/
- spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
- /* Portable SPI ISR code defined in the high level driver, note, it is
- a macro.*/
- _spi_isr_code(spip);
-}
-
-/**
- * @brief Shared TX1/TX2 DMA events service routine.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_tx_irq(edma_channel_t channel, void *p) {
- SPIDriver *spip = (SPIDriver *)p;
-
- (void)channel;
-
- /* Clearing TX channels state.*/
- edmaChannelStop(spip->tx1_channel);
- edmaChannelStop(spip->tx2_channel);
-
- /* If the TX FIFO is full then the push of the last frame is delagated to
- an interrupt handler else it is performed immediately. Both conditions
- can be true depending on the SPI speed and ISR latency.*/
- if (spip->dspi->SR.B.TFFF) {
- spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
- }
- else {
- spip->dspi->RSER.B.TFFFDIRS = 0;
- }
-}
-
-/**
- * @brief Shared ISR for DMA error events.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- * @param[in] esr content of the ESR register
- *
- * @notapi
- */
-static void spi_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr) {
- SPIDriver *spip = (SPIDriver *)p;
-
- (void)channel;
- (void)esr;
-
- /* Stops the DSPI and clears the queues.*/
- spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
- edmaChannelStop(spip->tx1_channel);
- edmaChannelStop(spip->tx2_channel);
- edmaChannelStop(spip->rx_channel);
-
- SPC5_SPI_DMA_ERROR_HOOK(spip);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI0_TFFF_HANDLER)
-#error "SPC5_DSPI0_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI0 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI0.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI0.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI0.PUSHR.R = (SPID1.config->pushr | SPID1.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI1_TFFF_HANDLER)
-#error "SPC5_DSPI1_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI1 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI1.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI1.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI1.PUSHR.R = (SPID2.config->pushr | SPID2.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI2_TFFF_HANDLER)
-#error "SPC5_DSPI2_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI2 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI2.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI2.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI2.PUSHR.R = (SPID3.config->pushr | SPID3.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI3_TFFF_HANDLER)
-#error "SPC5_DSPI3_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI3 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI3.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI3.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI3.PUSHR.R = (SPID4.config->pushr | SPID4.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI4_TFFF_HANDLER)
-#error "SPC5_DSPI4_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI4 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI4_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI4.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI4.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI4.PUSHR.R = (SPID5.config->pushr | SPID5.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if SPC5_SPI_USE_DSPI0
- /* Driver initialization.*/
- spiObjectInit(&SPID1);
- SPC5_DSPI0_ENABLE_CLOCK();
- SPID1.dspi = &SPC5_DSPI0;
- SPID1.tx1_channel = EDMA_ERROR;
- SPID1.tx2_channel = EDMA_ERROR;
- SPID1.rx_channel = EDMA_ERROR;
- SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI0_MCR;
- INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
- /* Driver initialization.*/
- SPC5_DSPI1_ENABLE_CLOCK();
- spiObjectInit(&SPID2);
- SPID2.dspi = &SPC5_DSPI1;
- SPID2.tx1_channel = EDMA_ERROR;
- SPID2.tx2_channel = EDMA_ERROR;
- SPID2.rx_channel = EDMA_ERROR;
- SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI1_MCR;
- INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
- /* Driver initialization.*/
- spiObjectInit(&SPID3);
- SPC5_DSPI2_ENABLE_CLOCK();
- SPID3.dspi = &SPC5_DSPI2;
- SPID3.tx1_channel = EDMA_ERROR;
- SPID3.tx2_channel = EDMA_ERROR;
- SPID3.rx_channel = EDMA_ERROR;
- SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI2_MCR;
- INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
- /* Driver initialization.*/
- spiObjectInit(&SPID4);
- SPC5_DSPI3_ENABLE_CLOCK();
- SPID4.dspi = &SPC5_DSPI3;
- SPID4.tx1_channel = EDMA_ERROR;
- SPID4.tx2_channel = EDMA_ERROR;
- SPID4.rx_channel = EDMA_ERROR;
- SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI3_MCR;
- INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
- /* Driver initialization.*/
- spiObjectInit(&SPID5);
- SPC5_DSPI4_ENABLE_CLOCK();
- SPID5.dspi = &SPC5_DSPI4;
- SPID5.tx1_channel = EDMA_ERROR;
- SPID5.tx2_channel = EDMA_ERROR;
- SPID5.rx_channel = EDMA_ERROR;
- SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI4_MCR;
- INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI4 */
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
- "spi_lld_start(), #1", "invalid PUSHR bits specified");
-
- if (spip->state == SPI_STOP) {
- /* Enables the peripheral.*/
-
-#if SPC5_SPI_USE_DSPI0
- if (&SPID1 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi0_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi0_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
- if (&SPID2 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi1_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi1_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
- if (&SPID3 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi2_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi2_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
- if (&SPID4 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi3_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi3_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
- if (&SPID5 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi4_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi4_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi4_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI5 */
-
- chDbgAssert((spip->tx1_channel != EDMA_ERROR) &&
- (spip->tx2_channel != EDMA_ERROR) &&
- (spip->rx_channel != EDMA_ERROR),
- "spi_lld_start(), #2", "channel cannot be allocated");
- }
-
- /* Configures the peripheral.*/
- spip->dspi->MCR.B.MDIS = 0;
- spip->dspi->CTAR[0].R = spip->config->ctar0;
- spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
- SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
- spip->dspi->SR.R = spip->dspi->SR.R;
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- if (spip->state == SPI_READY) {
- /* Releases the allocated EDMA channels.*/
- edmaChannelRelease(spip->tx1_channel);
- edmaChannelRelease(spip->tx2_channel);
- edmaChannelRelease(spip->rx_channel);
-
- /* Resets the peripheral.*/
- spip->dspi->CTAR[0].R = 0;
- spip->dspi->RSER.R = 0;
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.R |= SPC5_MCR_HALT |
- SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
- spip->dspi->MCR.B.MDIS = 1;
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle words on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx_ignore(spip, n);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill_ignore(spip, n);
- }
- else {
- spi_start_dma_tx_ignore(spip, n);
- }
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx8(spip, n, rxbuf);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill8(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx8(spip, n, txbuf);
- }
- }
- else {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx16(spip, n, rxbuf);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill16(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx16(spip, n, txbuf);
- }
- }
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx_ignore(spip, n);
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill8(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx8(spip, n, txbuf);
- }
- }
- else {
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill16(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx16(spip, n, txbuf);
- }
- }
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx8(spip, n, rxbuf);
- }
- else {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx16(spip, n, rxbuf);
- }
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill_ignore(spip, n);
- }
- else {
- spi_start_dma_tx_ignore(spip, n);
- }
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
- uint32_t popr;
-
- spip->dspi->MCR.B.HALT = 0;
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr |
- (uint32_t)frame) & ~SPC5_PUSHR_CONT;
- while (!spip->dspi->SR.B.RFDF)
- ;
- popr = spip->dspi->POPR.R;
- spip->dspi->MCR.B.HALT = 1;
- return (uint16_t)popr;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h deleted file mode 100644 index 1e2e9fd1c..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h +++ /dev/null @@ -1,532 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/DSPI_v1/spi_lld.h
- * @brief SPC5xx SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-#include "spc5_dspi.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SPID1 driver enable switch.
- * @details If set to @p TRUE the support for DSPI0 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI0) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI0 FALSE
-#endif
-
-/**
- * @brief SPID2 driver enable switch.
- * @details If set to @p TRUE the support for DSPI1 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI1 FALSE
-#endif
-
-/**
- * @brief SPID3 driver enable switch.
- * @details If set to @p TRUE the support for DSPI2 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI2) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI2 FALSE
-#endif
-
-/**
- * @brief SPID4 driver enable switch.
- * @details If set to @p TRUE the support for DSPI3 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI3) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI3 FALSE
-#endif
-
-/**
- * @brief SPID5 driver enable switch.
- * @details If set to @p TRUE the support for DSPI4 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI4 FALSE
-#endif
-
-/**
- * @brief DSPI0 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI1 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSP2 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI3 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI4 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI0 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI1 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI2 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI3 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI4 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief SPI DMA error hook.
- */
-#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
-#endif
-
-/**
- * @brief DSPI0 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI1 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI2 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI3 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI4 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI2 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI2 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI3 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI3 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI4 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI4 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !SPC5_HAS_DSPI0
-#error "DSPI0 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !SPC5_HAS_DSPI1
-#error "DSPI1 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !SPC5_HAS_DSPI2
-#error "DSPI2 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !SPC5_HAS_DSPI3
-#error "DSPI3 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !SPC5_HAS_DSPI4
-#error "DSPI4 not present in the selected device"
-#endif
-
-#if !SPC5_SPI_USE_DSPI0 && !SPC5_SPI_USE_DSPI1 && \
- !SPC5_SPI_USE_DSPI2 && !SPC5_SPI_USE_DSPI3 && \
- !SPC5_SPI_USE_DSPI4
-#error "SPI driver activated but no DSPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Operation complete callback.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number.
- */
- uint16_t sspad;
- /**
- * @brief DSPI CTAR0 value for this session.
- */
- uint32_t ctar0;
- /**
- * @brief DSPI PUSHR command for this session.
- * @note Only CTAR0 can be referenced, the other CTARs are not
- * initialized. The data part must be left to zero.
- */
- uint32_t pushr;
-} SPIConfig;
-
-/**
- * @brief Structure representing an SPI driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- Thread *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the DSPI registers block.
- */
- struct spc5_dspi *dspi;
- /**
- * @brief EDMA channel used for data memory to memory copy.
- */
- edma_channel_t tx1_channel;
- /**
- * @brief EDMA channel used for transmit.
- */
- edma_channel_t tx2_channel;
- /**
- * @brief EDMA channel used for receive.
- */
- edma_channel_t rx_channel;
- /**
- * @brief Last frame of a transmission sequence.
- */
- uint32_t tx_last;
- /**
- * @brief TX intermediate buffer.
- * @note This field is written by the TX1 DMA channel and read by the
- * TX2 DMA channel.
- */
- uint32_t tx_intbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !defined(__DOXYGEN__)
-extern SPIDriver SPID3;
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !defined(__DOXYGEN__)
-extern SPIDriver SPID4;
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !defined(__DOXYGEN__)
-extern SPIDriver SPID5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c deleted file mode 100644 index 7aad4027f..000000000 --- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c +++ /dev/null @@ -1,1402 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/spc5_edma.c
- * @brief EDMA helper driver code.
- *
- * @addtogroup SPC5xx_EDMA
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if SPC5_HAS_EDMA
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES};
-#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
-static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES};
-#endif
-#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
-static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES};
-static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES};
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Configurations for the various EDMA channels.
- */
-static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief EDMA (channels 0..31) error interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector10) {
- edma_channel_t channel;
- uint32_t erl, esr = SPC5_EDMA.ESR.R;
-
- CH_IRQ_PROLOGUE();
-
- /* Scanning for errors.*/
- channel = 0;
- while (((erl = SPC5_EDMA.ERL.R) != 0) &&
- (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) {
- if ((erl & (1U << channel)) != 0) {
- /* Error flag cleared.*/
- SPC5_EDMA.CER.R = channel;
-
- /* If the channel is not associated then the error is simply discarded
- else the error callback is invoked.*/
- if ((channels[channel] != NULL) &&
- (channels[channel]->dma_error_func != NULL))
- channels[channel]->dma_error_func(channel,
- channels[channel]->dma_param,
- esr);
- channel++;
- }
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 0 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector11) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[0] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 0;
- channels[0]->dma_func(0, channels[0]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 1 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector12) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[1] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 1;
- channels[1]->dma_func(1, channels[1]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 2 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector13) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[2] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 2;
- channels[2]->dma_func(2, channels[2]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 3 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector14) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[3] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 3;
- channels[3]->dma_func(3, channels[3]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 4 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector15) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[4] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 4;
- channels[4]->dma_func(4, channels[4]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 5 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector16) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[5] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 5;
- channels[5]->dma_func(5, channels[5]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 6 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector17) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[6] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 6;
- channels[6]->dma_func(6, channels[6]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 7 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector18) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[7] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 7;
- channels[7]->dma_func(7, channels[7]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 8 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector19) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[8] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 8;
- channels[8]->dma_func(8, channels[8]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 9 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector20) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[9] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 9;
- channels[9]->dma_func(9, channels[9]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 10 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector21) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[10] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 10;
- channels[10]->dma_func(10, channels[10]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 11 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector22) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[11] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 11;
- channels[11]->dma_func(11, channels[11]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 12 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector23) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[12] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 12;
- channels[12]->dma_func(12, channels[12]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 13 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector24) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[13] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 13;
- channels[13]->dma_func(13, channels[13]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 14 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector25) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[14] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 14;
- channels[14]->dma_func(14, channels[14]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 15 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector26) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[15] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 15;
- channels[15]->dma_func(15, channels[15]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
-/**
- * @brief EDMA channel 16 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector27) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[16] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 16;
- channels[16]->dma_func(16, channels[16]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 17 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector28) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[17] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 17;
- channels[17]->dma_func(17, channels[17]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 18 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector29) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[18] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 18;
- channels[18]->dma_func(18, channels[18]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 19 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector30) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[19] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 19;
- channels[19]->dma_func(19, channels[19]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 20 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector31) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[20] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 20;
- channels[20]->dma_func(20, channels[20]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 21 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector32) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[21] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 21;
- channels[21]->dma_func(21, channels[21]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 22 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector33) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[22] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 22;
- channels[22]->dma_func(22, channels[22]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 23 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector34) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[23] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 23;
- channels[23]->dma_func(23, channels[23]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 24 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector35) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[24] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 24;
- channels[24]->dma_func(24, channels[24]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 25 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector36) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[25] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 25;
- channels[25]->dma_func(25, channels[25]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 26 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector37) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[26] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 26;
- channels[26]->dma_func(26, channels[26]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 27 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector38) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[27] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 27;
- channels[27]->dma_func(27, channels[27]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 28 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector39) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[28] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 28;
- channels[28]->dma_func(28, channels[28]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 29 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector40) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[29] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 29;
- channels[29]->dma_func(29, channels[29]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 30 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector41) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[30] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 30;
- channels[30]->dma_func(30, channels[30]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 31 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector42) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[31] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 31;
- channels[31]->dma_func(31, channels[31]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
-/**
- * @brief EDMA (channels 32..64) error interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector210) {
- edma_channel_t channel;
- uint32_t erh, esr = SPC5_EDMA.ESR.R;
-
- CH_IRQ_PROLOGUE();
-
- /* Scanning for errors.*/
- channel = 32;
- while (((erh = SPC5_EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {
-
- if ((erh & (1U << (channel - 32))) != 0) {
- /* Error flag cleared.*/
- SPC5_EDMA.CER.R = channel;
-
- /* If the channel is not associated then the error is simply discarded
- else the error callback is invoked.*/
- if ((channels[channel] != NULL) &&
- (channels[channel]->dma_error_func != NULL))
- channels[channel]->dma_error_func(channel,
- channels[channel]->dma_param,
- esr);
- channel++;
- }
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 32 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector211) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[32] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 32;
- channels[32]->dma_func(32, channels[32]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 33 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector212) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[33] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 33;
- channels[33]->dma_func(33, channels[33]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 34 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector213) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[34] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 34;
- channels[34]->dma_func(34, channels[34]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 35 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector214) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[35] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 35;
- channels[35]->dma_func(35, channels[35]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 36 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector215) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[36] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 36;
- channels[36]->dma_func(36, channels[36]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 37 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector216) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[37] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 37;
- channels[37]->dma_func(37, channels[37]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 38 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector217) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[38] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 38;
- channels[38]->dma_func(38, channels[38]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 39 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector218) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[39] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 39;
- channels[39]->dma_func(39, channels[39]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 40 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector219) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[40] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 40;
- channels[40]->dma_func(40, channels[40]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 41 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector220) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[41] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 41;
- channels[41]->dma_func(41, channels[41]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 42 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector221) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[42] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 42;
- channels[42]->dma_func(42, channels[42]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 43 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector222) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[43] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 43;
- channels[43]->dma_func(43, channels[43]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 44 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector223) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[44] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 44;
- channels[44]->dma_func(44, channels[44]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 45 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector224) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[45] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 45;
- channels[45]->dma_func(45, channels[45]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 46 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector225) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[46] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 46;
- channels[46]->dma_func(46, channels[46]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 47 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector226) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[47] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 47;
- channels[47]->dma_func(47, channels[47]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 48 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector227) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[48] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 48;
- channels[48]->dma_func(48, channels[48]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 49 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector228) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[49] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 49;
- channels[49]->dma_func(49, channels[49]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 50 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector229) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[50] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 50;
- channels[50]->dma_func(50, channels[50]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 51 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector230) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[51] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 51;
- channels[51]->dma_func(51, channels[51]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 52 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector231) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[52] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 52;
- channels[52]->dma_func(52, channels[52]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 53 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector232) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[53] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 53;
- channels[53]->dma_func(53, channels[53]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 54 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector233) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[54] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 54;
- channels[54]->dma_func(54, channels[54]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 55 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector234) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[55] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 55;
- channels[55]->dma_func(55, channels[55]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 56 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector235) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[56] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 56;
- channels[56]->dma_func(56, channels[56]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 57 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector236) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[57] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 57;
- channels[57]->dma_func(57, channels[57]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 58 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector237) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[58] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 58;
- channels[58]->dma_func(58, channels[58]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 59 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector238) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[59] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 59;
- channels[59]->dma_func(59, channels[59]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 60 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector239) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[60] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 60;
- channels[60]->dma_func(60, channels[60]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 61 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector240) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[61] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 61;
- channels[61]->dma_func(61, channels[61]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 62 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector241) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[62] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 62;
- channels[62]->dma_func(62, channels[62]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief EDMA channel 63 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector242) {
-
- CH_IRQ_PROLOGUE();
-
- if (channels[63] == NULL) {
- SPC5_EDMA_ERROR_HANDLER();
- }
- SPC5_EDMA.CIRQR.R = 63;
- channels[63]->dma_func(63, channels[63]->dma_param);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_EDMA_NCHANNELS > 32 */
-#endif /* SPC5_EDMA_NCHANNELS > 16 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief EDMA driver initialization.
- *
- * @special
- */
-void edmaInit(void) {
- unsigned i;
-
- SPC5_EDMA.CR.R = SPC5_EDMA_CR_SETTING;
- SPC5_EDMA.ERQRL.R = 0x00000000;
- SPC5_EDMA.EEIRL.R = 0x00000000;
- SPC5_EDMA.IRQRL.R = 0xFFFFFFFF;
- SPC5_EDMA.ERL.R = 0xFFFFFFFF;
-#if SPC5_EDMA_NCHANNELS > 32
- SPC5_EDMA.ERQRH.R = 0x00000000;
- SPC5_EDMA.EEIRH.R = 0x00000000;
- SPC5_EDMA.IRQRH.R = 0xFFFFFFFF;
- SPC5_EDMA.ERH.R = 0xFFFFFFFF;
-#endif
- /* Initializing all the channels with a different priority withing the
- channels group.*/
- for (i = 0; i < 16; i++) {
- SPC5_EDMA.CPR[i].R = g0[i];
-#if SPC5_EDMA_NCHANNELS > 16
- SPC5_EDMA.CPR[i + 16].R = g1[i];
-#endif
-#if SPC5_EDMA_NCHANNELS > 32
- SPC5_EDMA.CPR[i + 32].R = g2[i];
- SPC5_EDMA.CPR[i + 48].R = g3[i];
-#endif
- }
-
- /* Error interrupt source.*/
- INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;
-
-#if defined(SPC5_EDMA_MUX_PCTL)
- /* DMA MUX PCTL setup, only if required.*/
- halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL);
-#endif
-}
-
-/**
- * @brief EDMA channel allocation.
- *
- * @param[in] ccfg channel configuration
- * @return The channel number.
- * @retval EDMA_ERROR if the channel cannot be allocated.
- *
- * @special
- */
-edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
-
- chDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16),
- "edmaChannelAllocate");
-
- /* If the channel is already taken then an error is returned.*/
- if (channels[ccfg->dma_channel] != NULL)
- return EDMA_ERROR; /* Already taken. */
-
-#if SPC5_EDMA_HAS_MUX
- /* Programming the MUX.*/
- SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |
- ccfg->dma_periph);
-#endif /* !SPC5_EDMA_HAS_MUX */
-
- /* Associating the configuration to the channel.*/
- channels[ccfg->dma_channel] = ccfg;
-
- /* If an error callback is defined then the error interrupt source is
- enabled for the channel.*/
- if (ccfg->dma_error_func != NULL)
- SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel;
-
- /* Setting up IRQ priority for the selected channel.*/
- INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio;
-
- return ccfg->dma_channel;
-}
-
-/**
- * @brief EDMA channel release.
- *
- * @param[in] channel the channel number
- *
- * @special
- */
-void edmaChannelRelease(edma_channel_t channel) {
-
- chDbgCheck((channel >= 0) && (channel < SPC5_EDMA_NCHANNELS),
- "edmaChannelAllocate");
- chDbgAssert(channels[channel] != NULL,
- "edmaChannelRelease(), #1",
- "not allocated");
-
- /* Enforcing a stop.*/
- edmaChannelStop(channel);
-
-#if SPC5_EDMA_HAS_MUX
- /* Disabling the MUX slot.*/
- SPC5_DMAMUX.CHCONFIG[channel].R = 0;
-#endif
-
- /* Clearing ISR sources for the channel.*/
- SPC5_EDMA.CIRQR.R = channel;
- SPC5_EDMA.CEEIR.R = channel;
- SPC5_EDMA.CER.R = channel;
-
- /* The channels is flagged as available.*/
- channels[channel] = NULL;
-}
-
-#endif /* SPC5_HAS_EDMA */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h deleted file mode 100644 index e66574e4a..000000000 --- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h +++ /dev/null @@ -1,1004 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/spc5_edma.h
- * @brief EDMA helper driver header.
- *
- * @addtogroup SPC5xx_EDMA
- * @{
- */
-
-#ifndef _SPC5_EDMA_H_
-#define _SPC5_EDMA_H_
-
-#if SPC5_HAS_EDMA
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief EDMA channel allocation error.
- */
-#define EDMA_ERROR -1
-
-/**
- * @name EDMA CR register definitions
- * @{
- */
-#define EDMA_CR_CX (1U << 17)
-#define EDMA_CR_ECX (1U << 16)
-#define EDMA_CR_GRP3PRI_MASK (3U << 14)
-#define EDMA_CR_GRP3PRI(n) ((n) << 14)
-#define EDMA_CR_GRP2PRI_MASK (3U << 12)
-#define EDMA_CR_GRP2PRI(n) ((n) << 12)
-#define EDMA_CR_GRP1PRI_MASK (3U << 10)
-#define EDMA_CR_GRP1PRI(n) ((n) << 10)
-#define EDMA_CR_GRP0PRI_MASK (3U << 8)
-#define EDMA_CR_GRP0PRI(n) ((n) << 8)
-#define EDMA_CR_EMLM (1U << 7)
-#define EDMA_CR_CLM (1U << 6)
-#define EDMA_CR_HALT (1U << 5)
-#define EDMA_CR_HOE (1U << 4)
-#define EDMA_CR_ERGA (1U << 3)
-#define EDMA_CR_ERCA (1U << 2)
-#define EDMA_CR_EDBG (1U << 1)
-#define EDMA_CR_EBW (1U << 0)
-/** @} */
-
-/**
- * @name EDMA mode constants
- * @{
- */
-#define EDMA_TCD_MODE_START (1U << 0)
-#define EDMA_TCD_MODE_INT_END (1U << 1)
-#define EDMA_TCD_MODE_INT_HALF (1U << 2)
-#define EDMA_TCD_MODE_DREQ (1U << 3)
-#define EDMA_TCD_MODE_SG (1U << 4)
-#define EDMA_TCD_MODE_MELINK (1U << 5)
-#define EDMA_TCD_MODE_ACTIVE (1U << 6)
-#define EDMA_TCD_MODE_DONE (1U << 7)
-#define EDMA_TCD_MODE_MLINKCH_MASK (63U << 8)
-#define EDMA_TCD_MODE_MLINKCH(n) ((uint32_t)(n) << 8)
-#define EDMA_TCD_MODE_BWC_MASK (3U << 14)
-#define EDMA_TCD_MODE_BWC(n) ((uint32_t)(n) << 14)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief Default EDMA CR register initialization.
- */
-#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
-#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
- EDMA_CR_GRP2PRI(2) | \
- EDMA_CR_GRP1PRI(1) | \
- EDMA_CR_GRP0PRI(0) | \
- EDMA_CR_ERGA)
-#endif
-
-/**
- * @brief Static priorities for channels group 0.
- */
-#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP0_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief Static priorities for channels group 1.
- */
-#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP1_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief Static priorities for channels group 2.
- */
-#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP2_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief Static priorities for channels group 3.
- */
-#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP3_PRIORITIES \
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief EDMA error handler IRQ priority.
- */
-#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_EDMA_ERROR_IRQ_PRIO 2
-#endif
-
-/**
- * @brief EDMA peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EDMA_MUX_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief EDMA critical error handler, must not return.
- */
-#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
-#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of and eDMA channel number.
- */
-typedef int32_t edma_channel_t;
-
-/**
- * @brief Type of an eDMA TCD.
- */
-typedef struct {
- union {
- uint32_t word[8];
- };
-} edma_tcd_t;
-
-/**
- * @brief Type of an eDMA peripheral.
- */
-typedef struct {
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :14;
- vuint32_t CX :1;
- vuint32_t ECX :1;
- vuint32_t GRP3PRI :2;
- vuint32_t GRP2PRI :2;
- vuint32_t GRP1PRI :2;
- vuint32_t GRP0PRI :2;
- vuint32_t EMLM :1;
- vuint32_t CLM :1;
- vuint32_t HALT :1;
- vuint32_t HOE :1;
- vuint32_t ERGA :1;
- vuint32_t ERCA :1;
- vuint32_t EDBG :1;
- vuint32_t :1;
- } B;
- } CR; /* DMA Control Register @baseaddress + 0x0 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t VLD :1;
- vuint32_t :14;
- vuint32_t ECX :1;
- vuint32_t GPE :1;
- vuint32_t CPE :1;
- vuint32_t ERRCHN :6;
- vuint32_t SAE :1;
- vuint32_t SOE :1;
- vuint32_t DAE :1;
- vuint32_t DOE :1;
- vuint32_t NCE :1;
- vuint32_t SGE :1;
- vuint32_t SBE :1;
- vuint32_t DBE :1;
- } B;
- } ESR; /* Error Status Register @baseaddress + 0x4 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t ERQ63 :1;
- vuint32_t ERQ62 :1;
- vuint32_t ERQ61 :1;
- vuint32_t ERQ60 :1;
- vuint32_t ERQ59 :1;
- vuint32_t ERQ58 :1;
- vuint32_t ERQ57 :1;
- vuint32_t ERQ56 :1;
- vuint32_t ERQ55 :1;
- vuint32_t ERQ54 :1;
- vuint32_t ERQ53 :1;
- vuint32_t ERQ52 :1;
- vuint32_t ERQ51 :1;
- vuint32_t ERQ50 :1;
- vuint32_t ERQ49 :1;
- vuint32_t ERQ48 :1;
- vuint32_t ERQ47 :1;
- vuint32_t ERQ46 :1;
- vuint32_t ERQ45 :1;
- vuint32_t ERQ44 :1;
- vuint32_t ERQ43 :1;
- vuint32_t ERQ42 :1;
- vuint32_t ERQ41 :1;
- vuint32_t ERQ40 :1;
- vuint32_t ERQ39 :1;
- vuint32_t ERQ38 :1;
- vuint32_t ERQ37 :1;
- vuint32_t ERQ36 :1;
- vuint32_t ERQ35 :1;
- vuint32_t ERQ34 :1;
- vuint32_t ERQ33 :1;
- vuint32_t ERQ32 :1;
- } B;
- } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/
-
- union {
- vuint32_t R;
- struct {
- vuint32_t ERQ31 :1;
- vuint32_t ERQ30 :1;
- vuint32_t ERQ29 :1;
- vuint32_t ERQ28 :1;
- vuint32_t ERQ27 :1;
- vuint32_t ERQ26 :1;
- vuint32_t ERQ25 :1;
- vuint32_t ERQ24 :1;
- vuint32_t ERQ23 :1;
- vuint32_t ERQ22 :1;
- vuint32_t ERQ21 :1;
- vuint32_t ERQ20 :1;
- vuint32_t ERQ19 :1;
- vuint32_t ERQ18 :1;
- vuint32_t ERQ17 :1;
- vuint32_t ERQ16 :1;
- vuint32_t ERQ15 :1;
- vuint32_t ERQ14 :1;
- vuint32_t ERQ13 :1;
- vuint32_t ERQ12 :1;
- vuint32_t ERQ11 :1;
- vuint32_t ERQ10 :1;
- vuint32_t ERQ09 :1;
- vuint32_t ERQ08 :1;
- vuint32_t ERQ07 :1;
- vuint32_t ERQ06 :1;
- vuint32_t ERQ05 :1;
- vuint32_t ERQ04 :1;
- vuint32_t ERQ03 :1;
- vuint32_t ERQ02 :1;
- vuint32_t ERQ01 :1;
- vuint32_t ERQ00 :1;
- } B;
- } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/
-
- union {
- vuint32_t R;
- struct {
-
- vuint32_t EEI63 :1;
- vuint32_t EEI62 :1;
- vuint32_t EEI61 :1;
- vuint32_t EEI60 :1;
- vuint32_t EEI59 :1;
- vuint32_t EEI58 :1;
- vuint32_t EEI57 :1;
- vuint32_t EEI56 :1;
- vuint32_t EEI55 :1;
- vuint32_t EEI54 :1;
- vuint32_t EEI53 :1;
- vuint32_t EEI52 :1;
- vuint32_t EEI51 :1;
- vuint32_t EEI50 :1;
- vuint32_t EEI49 :1;
- vuint32_t EEI48 :1;
- vuint32_t EEI47 :1;
- vuint32_t EEI46 :1;
- vuint32_t EEI45 :1;
- vuint32_t EEI44 :1;
- vuint32_t EEI43 :1;
- vuint32_t EEI42 :1;
- vuint32_t EEI41 :1;
- vuint32_t EEI40 :1;
- vuint32_t EEI39 :1;
- vuint32_t EEI38 :1;
- vuint32_t EEI37 :1;
- vuint32_t EEI36 :1;
- vuint32_t EEI35 :1;
- vuint32_t EEI34 :1;
- vuint32_t EEI33 :1;
- vuint32_t EEI32 :1;
- } B;
- } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
-
- union {
- vuint32_t R;
- struct {
- vuint32_t EEI31 :1;
- vuint32_t EEI30 :1;
- vuint32_t EEI29 :1;
- vuint32_t EEI28 :1;
- vuint32_t EEI27 :1;
- vuint32_t EEI26 :1;
- vuint32_t EEI25 :1;
- vuint32_t EEI24 :1;
- vuint32_t EEI23 :1;
- vuint32_t EEI22 :1;
- vuint32_t EEI21 :1;
- vuint32_t EEI20 :1;
- vuint32_t EEI19 :1;
- vuint32_t EEI18 :1;
- vuint32_t EEI17 :1;
- vuint32_t EEI16 :1;
- vuint32_t EEI15 :1;
- vuint32_t EEI14 :1;
- vuint32_t EEI13 :1;
- vuint32_t EEI12 :1;
- vuint32_t EEI11 :1;
- vuint32_t EEI10 :1;
- vuint32_t EEI09 :1;
- vuint32_t EEI08 :1;
- vuint32_t EEI07 :1;
- vuint32_t EEI06 :1;
- vuint32_t EEI05 :1;
- vuint32_t EEI04 :1;
- vuint32_t EEI03 :1;
- vuint32_t EEI02 :1;
- vuint32_t EEI01 :1;
- vuint32_t EEI00 :1;
- } B;
- } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t SERQ :7;
- } B;
- } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t CERQ :7;
- } B;
- } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t SEEI :7;
- } B;
- } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t CEEI :7;
- } B;
- } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t CINT :7;
- } B;
- } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t CERR :7;
- } B;
- } CER; /* DMA Clear error Register @baseaddress + 0x1D */
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t SSB :7;
- } B;
- } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */
-
- union {
- vuint8_t R;
- struct {
- vuint8_t NOP :1;
- vuint8_t CDSB :7;
- } B;
- } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t INT63 :1;
- vuint32_t INT62 :1;
- vuint32_t INT61 :1;
- vuint32_t INT60 :1;
- vuint32_t INT59 :1;
- vuint32_t INT58 :1;
- vuint32_t INT57 :1;
- vuint32_t INT56 :1;
- vuint32_t INT55 :1;
- vuint32_t INT54 :1;
- vuint32_t INT53 :1;
- vuint32_t INT52 :1;
- vuint32_t INT51 :1;
- vuint32_t INT50 :1;
- vuint32_t INT49 :1;
- vuint32_t INT48 :1;
- vuint32_t INT47 :1;
- vuint32_t INT46 :1;
- vuint32_t INT45 :1;
- vuint32_t INT44 :1;
- vuint32_t INT43 :1;
- vuint32_t INT42 :1;
- vuint32_t INT41 :1;
- vuint32_t INT40 :1;
- vuint32_t INT39 :1;
- vuint32_t INT38 :1;
- vuint32_t INT37 :1;
- vuint32_t INT36 :1;
- vuint32_t INT35 :1;
- vuint32_t INT34 :1;
- vuint32_t INT33 :1;
- vuint32_t INT32 :1;
- } B;
- } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t INT31 :1;
- vuint32_t INT30 :1;
- vuint32_t INT29 :1;
- vuint32_t INT28 :1;
- vuint32_t INT27 :1;
- vuint32_t INT26 :1;
- vuint32_t INT25 :1;
- vuint32_t INT24 :1;
- vuint32_t INT23 :1;
- vuint32_t INT22 :1;
- vuint32_t INT21 :1;
- vuint32_t INT20 :1;
- vuint32_t INT19 :1;
- vuint32_t INT18 :1;
- vuint32_t INT17 :1;
- vuint32_t INT16 :1;
- vuint32_t INT15 :1;
- vuint32_t INT14 :1;
- vuint32_t INT13 :1;
- vuint32_t INT12 :1;
- vuint32_t INT11 :1;
- vuint32_t INT10 :1;
- vuint32_t INT09 :1;
- vuint32_t INT08 :1;
- vuint32_t INT07 :1;
- vuint32_t INT06 :1;
- vuint32_t INT05 :1;
- vuint32_t INT04 :1;
- vuint32_t INT03 :1;
- vuint32_t INT02 :1;
- vuint32_t INT01 :1;
- vuint32_t INT00 :1;
- } B;
- } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t ERR63 :1;
- vuint32_t ERR62 :1;
- vuint32_t ERR61 :1;
- vuint32_t ERR60 :1;
- vuint32_t ERR59 :1;
- vuint32_t ERR58 :1;
- vuint32_t ERR57 :1;
- vuint32_t ERR56 :1;
- vuint32_t ERR55 :1;
- vuint32_t ERR54 :1;
- vuint32_t ERR53 :1;
- vuint32_t ERR52 :1;
- vuint32_t ERR51 :1;
- vuint32_t ERR50 :1;
- vuint32_t ERR49 :1;
- vuint32_t ERR48 :1;
- vuint32_t ERR47 :1;
- vuint32_t ERR46 :1;
- vuint32_t ERR45 :1;
- vuint32_t ERR44 :1;
- vuint32_t ERR43 :1;
- vuint32_t ERR42 :1;
- vuint32_t ERR41 :1;
- vuint32_t ERR40 :1;
- vuint32_t ERR39 :1;
- vuint32_t ERR38 :1;
- vuint32_t ERR37 :1;
- vuint32_t ERR36 :1;
- vuint32_t ERR35 :1;
- vuint32_t ERR34 :1;
- vuint32_t ERR33 :1;
- vuint32_t ERR32 :1;
- } B;
- } ERH; /* DMA Error High @baseaddress + 0x28 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t ERR31 :1;
- vuint32_t ERR30 :1;
- vuint32_t ERR29 :1;
- vuint32_t ERR28 :1;
- vuint32_t ERR27 :1;
- vuint32_t ERR26 :1;
- vuint32_t ERR25 :1;
- vuint32_t ERR24 :1;
- vuint32_t ERR23 :1;
- vuint32_t ERR22 :1;
- vuint32_t ERR21 :1;
- vuint32_t ERR20 :1;
- vuint32_t ERR19 :1;
- vuint32_t ERR18 :1;
- vuint32_t ERR17 :1;
- vuint32_t ERR16 :1;
- vuint32_t ERR15 :1;
- vuint32_t ERR14 :1;
- vuint32_t ERR13 :1;
- vuint32_t ERR12 :1;
- vuint32_t ERR11 :1;
- vuint32_t ERR10 :1;
- vuint32_t ERR09 :1;
- vuint32_t ERR08 :1;
- vuint32_t ERR07 :1;
- vuint32_t ERR06 :1;
- vuint32_t ERR05 :1;
- vuint32_t ERR04 :1;
- vuint32_t ERR03 :1;
- vuint32_t ERR02 :1;
- vuint32_t ERR01 :1;
- vuint32_t ERR00 :1;
- } B;
- } ERL; /* DMA Error Low @baseaddress + 0x2C */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t HRS63 :1;
- vuint32_t HRS62 :1;
- vuint32_t HRS61 :1;
- vuint32_t HRS60 :1;
- vuint32_t HRS59 :1;
- vuint32_t HRS58 :1;
- vuint32_t HRS57 :1;
- vuint32_t HRS56 :1;
- vuint32_t HRS55 :1;
- vuint32_t HRS54 :1;
- vuint32_t HRS53 :1;
- vuint32_t HRS52 :1;
- vuint32_t HRS51 :1;
- vuint32_t HRS50 :1;
- vuint32_t HRS49 :1;
- vuint32_t HRS48 :1;
- vuint32_t HRS47 :1;
- vuint32_t HRS46 :1;
- vuint32_t HRS45 :1;
- vuint32_t HRS44 :1;
- vuint32_t HRS43 :1;
- vuint32_t HRS42 :1;
- vuint32_t HRS41 :1;
- vuint32_t HRS40 :1;
- vuint32_t HRS39 :1;
- vuint32_t HRS38 :1;
- vuint32_t HRS37 :1;
- vuint32_t HRS36 :1;
- vuint32_t HRS35 :1;
- vuint32_t HRS34 :1;
- vuint32_t HRS33 :1;
- vuint32_t HRS32 :1;
- } B;
- } HRSH; /* hardware request status high @baseaddress + 0x30 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t HRS31 :1;
- vuint32_t HRS30 :1;
- vuint32_t HRS29 :1;
- vuint32_t HRS28 :1;
- vuint32_t HRS27 :1;
- vuint32_t HRS26 :1;
- vuint32_t HRS25 :1;
- vuint32_t HRS24 :1;
- vuint32_t HRS23 :1;
- vuint32_t HRS22 :1;
- vuint32_t HRS21 :1;
- vuint32_t HRS20 :1;
- vuint32_t HRS19 :1;
- vuint32_t HRS18 :1;
- vuint32_t HRS17 :1;
- vuint32_t HRS16 :1;
- vuint32_t HRS15 :1;
- vuint32_t HRS14 :1;
- vuint32_t HRS13 :1;
- vuint32_t HRS12 :1;
- vuint32_t HRS11 :1;
- vuint32_t HRS10 :1;
- vuint32_t HRS09 :1;
- vuint32_t HRS08 :1;
- vuint32_t HRS07 :1;
- vuint32_t HRS06 :1;
- vuint32_t HRS05 :1;
- vuint32_t HRS04 :1;
- vuint32_t HRS03 :1;
- vuint32_t HRS02 :1;
- vuint32_t HRS01 :1;
- vuint32_t HRS00 :1;
- } B;
- } HRSL; /* hardware request status low @baseaddress + 0x34 */
-
- uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
-
- union {
- vuint8_t R;
- struct {
- vuint8_t ECP :1;
- vuint8_t DPA :1;
- vuint8_t GRPPRI :2;
- vuint8_t CHPRI :4;
- } B;
- } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */
-
- uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */
-
- edma_tcd_t TCD[64];
-} edma_t;
-
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
-/**
- * @brief Type of a DMA-MUX peripheral.
- */
-typedef struct {
- union {
- vuint8_t R;
- struct {
- vuint8_t ENBL:1;
- vuint8_t TRIG:1;
- vuint8_t SOURCE:6;
- } B;
- } CHCONFIG[SPC5_EDMA_NCHANNELS];
-} dma_mux_t;
-#endif /* SPC5_EDMA_HAS_MUX */
-
-/**
- * @brief DMA callback type.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- */
-typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
-
-/**
- * @brief DMA error callback type.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- * @param[in] esr content of the ESR register
- */
-typedef void (*edma_error_callback_t)(edma_channel_t channel,
- void *p,
- uint32_t esr);
-
-/**
- * @brief Type of an EDMA channel configuration structure.
- */
-typedef struct {
- edma_channel_t dma_channel; /**< @brief Channel to be allocated.*/
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
- uint8_t dma_periph; /**< @brief Peripheral to be
- associated to the channel. */
-#endif
- uint8_t dma_irq_prio; /**< @brief IRQ priority level for
- this channel. */
- edma_callback_t dma_func; /**< @brief Channel callback,
- can be NULL if not required. */
- edma_error_callback_t dma_error_func; /**< @brief Channel error callback,
- can be NULL if not required. */
- void *dma_param; /**< @brief Channel callback param. */
-} edma_channel_config_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Peripherals references
- *
- * @{
- */
-#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
-#define SPC5_EDMA (*(edma_t *)0xFFF44000U)
-#endif
-
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
-#define SPC5_DMAMUX (*(dma_mux_t *)0xFFFDC000UL)
-#endif
-/** @} */
-
-/**
- * @brief Returns the TCD address associated to a channel.
- *
- * @param[in] channel the channel number
- * @return A pointer to an @p edma_tcd_t structure.
- *
- * @api
- */
-#define edmaGetTCD(channel) ((edma_tcd_t *)&SPC5_EDMA.TCD[channel])
-
-/**
- * @brief Sets the word 0 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] src the source address
- *
- * @api
- */
-#define edmaTCDSetWord0(tcdp, src) \
- ((tcdp)->word[0] = (uint32_t)(src))
-
-/**
- * @brief Sets the word 1 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] ssize the source width
- * @param[in] dst the destination width
- * @param[in] soff the source increment value
- *
- * @api
- */
-#define edmaTCDSetWord1(tcdp, ssize, dsize, soff) \
- ((tcdp)->word[1] = (((uint32_t)(ssize) << 24) | \
- ((uint32_t)(dsize) << 16) | \
- ((uint32_t)(soff) << 0)))
-
-/**
- * @brief Sets the word 2 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] nbytes the inner counter value
- *
- * @api
- */
-#define edmaTCDSetWord2(tcdp, nbytes) \
- ((tcdp)->word[2] = (uint32_t)(nbytes))
-
-/**
- * @brief Sets the word 3 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] slast the adjustment value
- *
- * @api
- */
-#define edmaTCDSetWord3(tcdp, slast) \
- ((tcdp)->word[3] = (uint32_t)(slast))
-
-/**
- * @brief Sets the word 4 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] dst the destination address
- *
- * @api
- */
-#define edmaTCDSetWord4(tcdp, dst) \
- ((tcdp)->word[4] = (uint32_t)(dst))
-
-/**
- * @brief Sets the word 5 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] citer the current outer counter value
- * @param[in] doff the destination increment value
- *
- * @api
- */
-#define edmaTCDSetWord5(tcdp, citer, doff) \
- ((tcdp)->word[5] = (((uint32_t)(citer) << 16) | \
- ((uint32_t)(doff) << 0)))
-
-/**
- * @brief Sets the word 5 fields into a TCD.
- * @note Transfers are limited to 512 operations using this modality
- * (citer parameter).
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] linkch channel linked on minor loop counter
- * @param[in] citer the current outer counter value
- * @param[in] doff the destination increment value
- *
- * @api
- */
-#define edmaTCDSetWord5Linked(tcdp, linkch, citer, doff) \
- ((tcdp)->word[5] = (((uint32_t)0x80000000) | \
- ((uint32_t)(linkch) << 25) | \
- ((uint32_t)(citer) << 16) | \
- ((uint32_t)(doff) << 0)))
-
-/**
- * @brief Sets the word 6 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] dlast the adjustment value
- *
- * @api
- */
-#define edmaTCDSetWord6(tcdp, dlast) \
- ((tcdp)->word[6] = (uint32_t)(dlast))
-
-/**
- * @brief Sets the word 7 fields into a TCD.
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] biter the base outer counter value
- * @param[in] mode the mode value
- *
- * @api
- */
-#define edmaTCDSetWord7(tcdp, biter, mode) \
- ((tcdp)->word[7] = (((uint32_t)(biter) << 16) | \
- ((uint32_t)(mode) << 0)))
-
-/**
- * @brief Sets the word 7 fields into a TCD.
- * @note Transfers are limited to 512 operations using this modality
- * (biter parameter).
- *
- * @param[in] tcdp pointer to an @p edma_tcd_t structure
- * @param[in] linkch channel linked on minor loop counter
- * @param[in] biter the base outer counter value
- * @param[in] mode the mode value
- *
- * @api
- */
-#define edmaTCDSetWord7Linked(tcdp, linkch, biter, mode) \
- ((tcdp)->word[7] = (((uint32_t)0x80000000) | \
- ((uint32_t)(linkch) << 25) | \
- ((uint32_t)(biter) << 16) | \
- ((uint32_t)(mode) << 0)))
-
-/**
- * @brief Starts or restarts an EDMA channel.
- *
- * @param[in] channel the channel number
- *
- * @api
- */
-#define edmaChannelStart(channel) (SPC5_EDMA.SERQR.R = (channel))
-
-/**
- * @brief Stops an EDMA channel.
- *
- * @param[in] channel the channel number
- *
- * @api
- */
-#define edmaChannelStop(channel) { \
- SPC5_EDMA.CERQR.R = (channel); \
- SPC5_EDMA.CDSBR.R = (channel); \
-}
-
-/**
- * @brief EDMA channel setup.
- *
- * @param[in] channel eDMA channel number
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] soff source address offset
- * @param[in] doff destination address offset
- * @param[in] ssize source transfer size
- * @param[in] dsize destination transfer size
- * @param[in] nbytes minor loop count
- * @param[in] iter major loop count
- * @param[in] dlast last destination address adjustment
- * @param[in] slast last source address adjustment
- * @param[in] mode LSW of TCD register 7
- *
- * @api
- */
-#define edmaChannelSetup(channel, src, dst, soff, doff, ssize, dsize, \
- nbytes, iter, slast, dlast, mode) { \
- edma_tcd_t *tcdp = edmaGetTCD(channel); \
- edmaTCDSetWord0(tcdp, src); \
- edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
- edmaTCDSetWord2(tcdp, nbytes); \
- edmaTCDSetWord3(tcdp, slast); \
- edmaTCDSetWord4(tcdp, dst); \
- edmaTCDSetWord5(tcdp, iter, doff); \
- edmaTCDSetWord6(tcdp, dlast); \
- edmaTCDSetWord7(tcdp, iter, mode); \
-}
-
-/**
- * @brief EDMA channel setup with linked channel on both minor and major
- * loop counters.
- * @note Transfers are limited to 512 operations using this modality
- * (iter parameter).
- *
- * @param[in] channel eDMA channel number
- * @param[in] linkch channel linked on minor loop counter
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] soff source address offset
- * @param[in] doff destination address offset
- * @param[in] ssize source transfer size
- * @param[in] dsize destination transfer size
- * @param[in] nbytes minor loop count
- * @param[in] iter major loop count
- * @param[in] dlast last destination address adjustment
- * @param[in] slast last source address adjustment
- * @param[in] mode LSW of TCD register 7
- *
- * @api
- */
-#define edmaChannelSetupLinked(channel, linkch, src, dst, soff, \
- doff, ssize, dsize, nbytes, iter, \
- slast, dlast, mode) { \
- edma_tcd_t *tcdp = edmaGetTCD(channel); \
- edmaTCDSetWord0(tcdp, src); \
- edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
- edmaTCDSetWord2(tcdp, nbytes); \
- edmaTCDSetWord3(tcdp, slast); \
- edmaTCDSetWord4(tcdp, dst); \
- edmaTCDSetWord5Linked(tcdp, linkch, iter, doff); \
- edmaTCDSetWord6(tcdp, dlast); \
- edmaTCDSetWord7Linked(tcdp, linkch, iter, (mode) | \
- EDMA_TCD_MODE_MELINK | \
- EDMA_TCD_MODE_MLINKCH(linkch)); \
-}
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void edmaInit(void);
- edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg);
- void edmaChannelRelease(edma_channel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SPC5_HAS_EDMA */
-
-#endif /* _SPC5_EDMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c deleted file mode 100644 index cb479fa1b..000000000 --- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c +++ /dev/null @@ -1,744 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/EQADC_v1/adc_lld.c
- * @brief SPC5xx low level ADC driver code.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/* Some forward declarations.*/
-static void adc_serve_rfifo_irq(edma_channel_t channel, void *p);
-static void adc_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr);
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Calibration constant.
- * @details Ideal conversion result for 75%(VRH - VRL) minus 2.
- */
-#define ADC_IDEAL_RES75_2 12286
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief ADCD1 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/**
- * @brief ADCD2 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__)
-ADCDriver ADCD2;
-#endif
-
-/**
- * @brief ADCD3 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/**
- * @brief ADCD4 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
-ADCDriver ADCD4;
-#endif
-
-/**
- * @brief ADCD5 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__)
-ADCDriver ADCD5;
-#endif
-
-/**
- * @brief ADCD6 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__)
-ADCDriver ADCD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active ADC FIFOs.
- */
-static uint32_t adc_active_fifos;
-
-/**
- * @brief Static setup for input resistors.
- */
-static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR;
-
-#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO0.
- */
-static const edma_channel_config_t adc_cfifo0_dma_config = {
- 0, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD1
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO0.
- */
-static const edma_channel_config_t adc_rfifo0_dma_config = {
- 1, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD1
-};
-#endif /* SPC5_ADC_USE_ADC0_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO1.
- */
-static const edma_channel_config_t adc_cfifo1_dma_config = {
- 2, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD2
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO1.
- */
-static const edma_channel_config_t adc_rfifo1_dma_config = {
- 3, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD2
-};
-#endif /* SPC5_ADC_USE_ADC0_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO2.
- */
-static const edma_channel_config_t adc_cfifo2_dma_config = {
- 4, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD3
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO2.
- */
-static const edma_channel_config_t adc_rfifo2_dma_config = {
- 5, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD3
-};
-#endif /* SPC5_ADC_USE_ADC0_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO3.
- */
-static const edma_channel_config_t adc_cfifo3_dma_config = {
- 6, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD4
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO3.
- */
-static const edma_channel_config_t adc_rfifo3_dma_config = {
- 7, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD4
-};
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO4.
- */
-static const edma_channel_config_t adc_cfifo4_dma_config = {
- 8, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD5
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO4.
- */
-static const edma_channel_config_t adc_rfifo4_dma_config = {
- 9, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD5
-};
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for EQADC CFIFO5.
- */
-static const edma_channel_config_t adc_cfifo5_dma_config = {
- 10, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,
- NULL, adc_serve_dma_error_irq, &ADCD6
-};
-
-/**
- * @brief DMA configuration for EQADC RFIFO5.
- */
-static const edma_channel_config_t adc_rfifo5_dma_config = {
- 11, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,
- adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD6
-};
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
-/*===========================================================================*/
-/* Driver local functions and macros. */
-/*===========================================================================*/
-
-/**
- * @brief Unsigned two's complement.
- *
- * @param[in] n the value to be complemented
- *
- * @notapi
- */
-#define CPL2(n) ((~(uint32_t)(n)) + 1)
-
-/**
- * @brief Address of a CFIFO push register.
- *
- * @param[in] fifo the FIFO identifier
- *
- * @notapi
- */
-#define CFIFO_PUSH_ADDR(fifo) ((uint32_t *)(&EQADC.CFPR[fifo].R))
-
-/**
- * @brief Address of a RFIFO pop register.
- *
- * @param[in] fifo the FIFO identifier
- *
- * @notapi
- */
-#define RFIFO_POP_ADDR(fifo) (((uint16_t *)&EQADC.RFPR[fifo].R) + 1)
-
-/**
- * @brief Enables a CFIFO.
- *
- * @param[in] fifo the FIFO identifier
- * @param[in] cfcr CFCR register value
- * @param[in] idcr IDCR register value
- *
- * @notapi
- */
-static void cfifo_enable(adcfifo_t fifo, uint16_t cfcr, uint16_t idcr) {
-
- EQADC.CFCR[fifo].R = cfcr;
- EQADC.IDCR[fifo].R = idcr;
-}
-
-/**
- * @brief Disables a CFIFO and the associated resources.
- *
- * @param[in] fifo the FIFO identifier
- *
- * @notapi
- */
-static void cfifo_disable(adcfifo_t fifo) {
-
- /* Disables the CFIFO.*/
- EQADC.CFCR[fifo].R = EQADC_CFCR_MODE_DISABLED;
-
- /* Disables Interrupts and DMAs of the CFIFO.*/
- EQADC.IDCR[fifo].R = 0;
-
- /* Waits for the CFIFO to become idle.*/
- while ((EQADC.CFSR.R & (0xC0000000 >> (fifo * 2))) != 0)
- ;
-
- /* Invalidates the CFIFO.*/
- EQADC.CFCR[fifo].R = EQADC_CFCR_CFINV | EQADC_CFCR_MODE_DISABLED;
-
- /* Clears all Interrupts and eDMA flags for the CFIFO.*/
- EQADC.FISR[fifo].R = EQADC_FISR_CLEAR_MASK;
-
- /* Clears the Tx Count Registers for the CFIFO.*/
- EQADC.CFTCR[fifo].R = 0;
-}
-
-/**
- * @brief Pushes a command into the CFIFO0.
- *
- * @param[in] cmd the command
- *
- * @notapi
- */
-static void cfifo0_push_command(adccommand_t cmd) {
-
- while (EQADC.FISR[0].B.CFCTR >= 4)
- ;
- EQADC.CFPR[0].R = cmd;
-}
-
-/**
- * @brief Waits until the RFIFO0 contains the specified number of entries.
- *
- * @param[in] n number of entries
- *
- * @notapi
- */
-static void cfifo0_wait_rfifo(uint32_t n) {
-
- while (EQADC.FISR[0].B.RFCTR < n)
- ;
- EQADC.FISR[0].R = EQADC_FISR_CLEAR_MASK;
-}
-
-/**
- * @brief Reads a sample from the RFIFO0.
- *
- * @notapi
- */
-#define rfifo0_get_value() (EQADC.RFPR[0].R)
-
-/**
- * @brief Writes an internal ADC register.
- *
- * @param[in] adc the ADC unit
- * @param[in] reg the register index
- * @param[in] value value to be written into the register
- *
- * @notapi
- */
-#define adc_write_register(adc, reg, value) \
- cfifo0_push_command(EQADC_RW_WRITE | (adc) | EQADC_RW_REG_ADDR(reg) | \
- EQADC_RW_VALUE(value))
-
-
-/**
- * @brief Enables both ADCs.
- *
- * @notapi
- */
-static void adc_enable(void) {
-
- /* Both ADCs must be enabled because this sentence in the reference manual:
- "Both ADC0 and ADC1 of an eQADC module pair must be enabled before
- calibrating or using either ADC0 or ADC1 of the pair. Failure to
- enable both ADC0 and ADC1 of the pair can result in inaccurate
- conversions.".*/
- adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
- SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
- adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
- SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
-}
-
-/**
- * @brief Disables both ADCs.
- *
- * @notapi
- */
-static void adc_disable(void) {
-
- adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
- SPC5_ADC_CR_CLK_PS);
- adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
- SPC5_ADC_CR_CLK_PS);
-}
-
-/**
- * @brief Calibrates an ADC unit.
- *
- * @param[in] adc the ADC unit
- *
- * @notapi
- */
-static void adc_calibrate(uint32_t adc) {
- uint16_t res25, res75;
- uint32_t gcc, occ;
-
- /* Starts the calibration, write command messages to sample 25% and
- 75% VREF.*/
- cfifo0_push_command(0x00002C00 | adc); /* Vref 25%.*/
- cfifo0_push_command(0x00002B00 | adc); /* Vref 75%.*/
- cfifo0_wait_rfifo(2);
-
- /* Reads the results and compute calibration register values.*/
- res25 = rfifo0_get_value();
- res75 = rfifo0_get_value();
-
- gcc = 0x08000000UL / ((uint32_t)res75 - (uint32_t)res25);
- occ = (uint32_t)ADC_IDEAL_RES75_2 - ((gcc * (uint32_t)res75) >> 14);
-
- /* Loads the gain and offset values (default configuration, 12 bits).*/
- adc_write_register(adc, ADC_REG_GCCR, gcc);
- adc_write_register(adc, ADC_REG_OCCR, occ & 0xFFFF);
-
- /* Loads gain and offset values (alternate configuration 1, 10 bits).*/
- adc_write_register(adc, ADC_REG_AC1GCCR, gcc);
- adc_write_register(adc, ADC_REG_AC1OCCR, occ & 0xFFFF);
-
- /* Loads gain and offset values (alternate configuration 1, 8 bits).*/
- adc_write_register(adc, ADC_REG_AC2GCCR, gcc);
- adc_write_register(adc, ADC_REG_AC2OCCR, occ & 0xFFFF);
-}
-
-/**
- * @brief Calibrates an ADC unit.
- *
- * @param[in] adc the ADC unit
- *
- * @notapi
- */
-static void adc_setup_resistors(uint32_t adc) {
- unsigned i;
-
- for (i = 0; i < 8; i++)
- adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]);
-}
-
-/**
- * @brief Shared ISR for RFIFO DMA events.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- *
- * @notapi
- */
-static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) {
- ADCDriver *adcp = (ADCDriver *)p;
- edma_tcd_t *tcdp = edmaGetTCD(channel);
-
- if (adcp->grpp != NULL) {
- if ((tcdp->word[5] >> 16) != (tcdp->word[7] >> 16)) {
- /* Half transfer processing.*/
- _adc_isr_half_code(adcp);
- }
- else {
- /* Re-starting DMA channels if in circular mode.*/
- if (adcp->grpp->circular) {
- edmaChannelStart(adcp->rfifo_channel);
- edmaChannelStart(adcp->cfifo_channel);
- }
-
- /* Transfer complete processing.*/
- _adc_isr_full_code(adcp);
- }
- }
-}
-
-/**
- * @brief Shared ISR for CFIFO/RFIFO DMA error events.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- * @param[in] esr content of the ESR register
- *
- * @notapi
- */
-static void adc_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr) {
- ADCDriver *adcp = (ADCDriver *)p;
-
- (void)channel;
- (void)esr;
-
- _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
- /* FIFOs initially all not in use.*/
- adc_active_fifos = 0;
-
-#if SPC5_ADC_USE_ADC0_Q0
- /* Driver initialization.*/
- adcObjectInit(&ADCD1);
- ADCD1.cfifo_channel = EDMA_ERROR;
- ADCD1.rfifo_channel = EDMA_ERROR;
- ADCD1.fifo = ADC_FIFO_0;
-#endif /* SPC5_ADC_USE_EQADC_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1
- /* Driver initialization.*/
- adcObjectInit(&ADCD2);
- ADCD2.cfifo_channel = EDMA_ERROR;
- ADCD2.rfifo_channel = EDMA_ERROR;
- ADCD2.fifo = ADC_FIFO_1;
-#endif /* SPC5_ADC_USE_EQADC_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2
- /* Driver initialization.*/
- adcObjectInit(&ADCD3);
- ADCD3.cfifo_channel = EDMA_ERROR;
- ADCD3.rfifo_channel = EDMA_ERROR;
- ADCD3.fifo = ADC_FIFO_2;
-#endif /* SPC5_ADC_USE_EQADC_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3
- /* Driver initialization.*/
- adcObjectInit(&ADCD4);
- ADCD4.cfifo_channel = EDMA_ERROR;
- ADCD4.rfifo_channel = EDMA_ERROR;
- ADCD4.fifo = ADC_FIFO_3;
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4
- /* Driver initialization.*/
- adcObjectInit(&ADCD5);
- ADCD5.cfifo_channel = EDMA_ERROR;
- ADCD5.rfifo_channel = EDMA_ERROR;
- ADCD5.fifo = ADC_FIFO_4;
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5
- /* Driver initialization.*/
- adcObjectInit(&ADCD6);
- ADCD6.cfifo_channel = EDMA_ERROR;
- ADCD6.rfifo_channel = EDMA_ERROR;
- ADCD6.fifo = ADC_FIFO_5;
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
- /* Temporarily enables CFIFO0 for calibration and initialization.*/
- cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0);
- adc_enable();
-
- /* Calibration of both ADC units, programming alternate configs
- one and two for 10 and 8 bits operations, setting up pull up/down
- resistors.*/
-#if SPC5_ADC_USE_ADC0
- adc_calibrate(EQADC_RW_BN_ADC0);
- adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
- adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
- adc_setup_resistors(EQADC_RW_BN_ADC0);
-#endif
-#if SPC5_ADC_USE_ADC1
- adc_calibrate(EQADC_RW_BN_ADC1);
- adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
- adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
- adc_setup_resistors(EQADC_RW_BN_ADC1);
-#endif
-
- /* ADCs disabled until the driver is started by the application.*/
- adc_disable();
- cfifo_disable(ADC_FIFO_0);
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- chDbgAssert(adc_active_fifos < 6, "adc_lld_start(), #1", "too many FIFOs");
-
- if (adcp->state == ADC_STOP) {
- /* Enables the peripheral.*/
-#if SPC5_ADC_USE_ADC0_Q0
- if (&ADCD1 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo0_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo0_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC0_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1
- if (&ADCD2 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo1_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo1_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC0_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2
- if (&ADCD3 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo2_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo2_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC0_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3
- if (&ADCD4 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo3_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo3_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4
- if (&ADCD5 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo4_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo4_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5
- if (&ADCD6 == adcp) {
- adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo5_dma_config);
- adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo5_dma_config);
- adc_active_fifos++;
- }
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
- /* If this is the first FIFO activated then the ADC is enabled.*/
- if (adc_active_fifos == 1)
- adc_enable();
- }
-
- chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) &&
- (adcp->rfifo_channel != EDMA_ERROR),
- "adc_lld_start(), #2", "channel cannot be allocated");
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
- chDbgAssert(adc_active_fifos < 6, "adc_lld_stop(), #1", "too many FIFOs");
-
- if (adcp->state == ADC_READY) {
- /* Resets the peripheral.*/
-
- /* Releases the allocated EDMA channels.*/
- edmaChannelRelease(adcp->cfifo_channel);
- edmaChannelRelease(adcp->rfifo_channel);
-
- /* If it is the last active FIFO then the ADC is disable too.*/
- if (--adc_active_fifos == 0)
- adc_disable();
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- * @note Because an HW constraint the number of rows in the samples
- * array must not be greater than the preconfigured value in
- * the conversion group.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t bitoff;
-
- chDbgAssert(adcp->grpp->num_iterations >= adcp->depth,
- "adc_lld_start_conversion(), #1", "too many elements");
-
- /* Setting up CFIFO TCD parameters.*/
- edmaChannelSetup(adcp->cfifo_channel, /* channel. */
- adcp->grpp->commands, /* src. */
- CFIFO_PUSH_ADDR(adcp->fifo), /* dst. */
- 4, /* soff, advance by 4. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- (uint32_t)adcp->grpp->num_channels *
- (uint32_t)adcp->depth, /* iter. */
- CPL2((uint32_t)adcp->grpp->num_channels *
- (uint32_t)adcp->depth *
- sizeof(adccommand_t)), /* slast. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ); /* mode. */
-
- /* Setting up RFIFO TCD parameters.*/
- edmaChannelSetup(adcp->rfifo_channel, /* channel. */
- RFIFO_POP_ADDR(adcp->fifo), /* src. */
- adcp->samples, /* dst. */
- 0, /* soff, do not advance. */
- 2, /* doff, advance by two. */
- 1, /* ssize, 16 bits transfers.*/
- 1, /* dsize, 16 bits transfers.*/
- 2, /* nbytes, always two. */
- (uint32_t)adcp->grpp->num_channels *
- (uint32_t)adcp->depth, /* iter. */
- 0, /* slast, no source adjust. */
- CPL2((uint32_t)adcp->grpp->num_channels *
- (uint32_t)adcp->depth *
- sizeof(adcsample_t)), /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END |
- ((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0));/* mode.*/
-
- /* HW triggers setup.*/
- bitoff = 20 + ((uint32_t)adcp->fifo * 2);
- SIU.ETISR.R = (SIU.ETISR.R & ~(3U << bitoff)) |
- (adcp->grpp->tsel << bitoff);
- bitoff = (uint32_t)adcp->fifo * 5;
- SIU.ISEL3.R = (SIU.ISEL3.R & ~(31U << bitoff)) |
- (adcp->grpp->etsel << bitoff);
-
- /* Starting DMA channels.*/
- edmaChannelStart(adcp->rfifo_channel);
- edmaChannelStart(adcp->cfifo_channel);
-
- /* Enabling CFIFO, conversion starts.*/
- cfifo_enable(adcp->fifo, adcp->grpp->cfcr,
- EQADC_IDCR_CFFE | EQADC_IDCR_CFFS |
- EQADC_IDCR_RFDE | EQADC_IDCR_RFDS);
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
- /* Stopping DMA channels.*/
- edmaChannelStop(adcp->cfifo_channel);
- edmaChannelStop(adcp->rfifo_channel);
-
- /* Disabling CFIFO.*/
- cfifo_disable(adcp->fifo);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h deleted file mode 100644 index f8713c9e8..000000000 --- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h +++ /dev/null @@ -1,663 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/EQADC_v1/adc_lld.c
- * @brief SPC5xx low level ADC driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Analog channel identifiers
- * @{
- */
-#define ADC_CHN_AN0 0U
-#define ADC_CHN_AN1 1U
-#define ADC_CHN_AN2 2U
-#define ADC_CHN_AN3 3U
-#define ADC_CHN_AN4 4U
-#define ADC_CHN_AN5 5U
-#define ADC_CHN_AN6 6U
-#define ADC_CHN_AN7 7U
-#define ADC_CHN_AN8 8U
-#define ADC_CHN_AN9 9U
-#define ADC_CHN_AN10 10U
-#define ADC_CHN_AN11 11U
-#define ADC_CHN_AN12 12U
-#define ADC_CHN_AN13 13U
-#define ADC_CHN_AN14 14U
-#define ADC_CHN_AN15 15U
-#define ADC_CHN_AN16 16U
-#define ADC_CHN_AN17 17U
-#define ADC_CHN_AN18 18U
-#define ADC_CHN_AN19 19U
-#define ADC_CHN_AN20 20U
-#define ADC_CHN_AN21 21U
-#define ADC_CHN_AN22 22U
-#define ADC_CHN_AN23 23U
-#define ADC_CHN_AN24 24U
-#define ADC_CHN_AN25 25U
-#define ADC_CHN_AN26 26U
-#define ADC_CHN_AN27 27U
-#define ADC_CHN_AN28 28U
-#define ADC_CHN_AN29 29U
-#define ADC_CHN_AN30 30U
-#define ADC_CHN_AN31 31U
-#define ADC_CHN_AN32 32U
-#define ADC_CHN_AN33 33U
-#define ADC_CHN_AN34 34U
-#define ADC_CHN_AN35 35U
-#define ADC_CHN_AN36 36U
-#define ADC_CHN_AN37 37U
-#define ADC_CHN_AN38 38U
-#define ADC_CHN_AN39 39U
-#define ADC_CHN_VRH 40U
-#define ADC_CHN_VRL 41U
-#define ADC_CHN_VREF50 42U
-#define ADC_CHN_VREF75 43U
-#define ADC_CHN_VREF25 44U
-#define ADC_CHN_BANDGAP 45U
-#define ADC_CHN_DAN0 96U
-#define ADC_CHN_DAN1 97U
-#define ADC_CHN_DAN2 98U
-#define ADC_CHN_DAN3 99U
-#define ADC_CHN_TEMP_SENSOR 128U
-#define ADC_CHN_SPARE 129U
-/** @} */
-
-/**
- * @name Internal registers indexes
- * @{
- */
-#define ADC_REG_CR 0x1
-#define ADC_REG_TSCR 0x2
-#define ADC_REG_TBCR 0x3
-#define ADC_REG_GCCR 0x4
-#define ADC_REG_OCCR 0x5
-#define ADC_REG_AC1GCCR 0x31
-#define ADC_REG_AC1OCCR 0x32
-#define ADC_REG_AC2GCCR 0x35
-#define ADC_REG_AC2OCCR 0x36
-#define ADC_REG_AC1CR 0x30
-#define ADC_REG_AC2CR 0x34
-#define ADC_REG_AC3CR 0x38
-#define ADC_REG_AC4CR 0x3C
-#define ADC_REG_AC5CR 0x40
-#define ADC_REG_AC6CR 0x44
-#define ADC_REG_AC7CR 0x48
-#define ADC_REG_AC8CR 0x4C
-#define ADC_REG_PUDCR(n) (0x70 + (n))
-#define ADC_REG_PUDCR0 0x70UL
-#define ADC_REG_PUDCR1 0x71UL
-#define ADC_REG_PUDCR2 0x72UL
-#define ADC_REG_PUDCR3 0x73UL
-#define ADC_REG_PUDCR4 0x74UL
-#define ADC_REG_PUDCR5 0x75UL
-#define ADC_REG_PUDCR6 0x76UL
-#define ADC_REG_PUDCR7 0x77UL
-/** @} */
-
-/**
- * @name EQADC IDCR registers definitions
- * @{
- */
-#define EQADC_IDCR_NCIE (1U << 15)
-#define EQADC_IDCR_TORIE (1U << 14)
-#define EQADC_IDCR_PIE (1U << 13)
-#define EQADC_IDCR_EOQIE (1U << 12)
-#define EQADC_IDCR_CFUIE (1U << 11)
-#define EQADC_IDCR_CFFE (1U << 9)
-#define EQADC_IDCR_CFFS (1U << 8)
-#define EQADC_IDCR_RFOIE (1U << 3)
-#define EQADC_IDCR_RFDE (1U << 1)
-#define EQADC_IDCR_RFDS (1U << 0)
-/** @} */
-
-/**
- * @name EQADC CFCR registers definitions
- * @{
- */
-#define EQADC_CFCR_CFEEE0 (1U << 12)
-#define EQADC_CFCR_STRME0 (1U << 11)
-#define EQADC_CFCR_SSE (1U << 10)
-#define EQADC_CFCR_CFINV (1U << 9)
-#define EQADC_CFCR_MODE_MASK (15U << 4)
-#define EQADC_CFCR_MODE(n) ((n) << 4)
-#define EQADC_CFCR_MODE_DISABLED EQADC_CFCR_MODE(0)
-#define EQADC_CFCR_MODE_SWSS EQADC_CFCR_MODE(1)
-#define EQADC_CFCR_MODE_HWSS_LL EQADC_CFCR_MODE(2)
-#define EQADC_CFCR_MODE_HWSS_HL EQADC_CFCR_MODE(3)
-#define EQADC_CFCR_MODE_HWSS_FE EQADC_CFCR_MODE(4)
-#define EQADC_CFCR_MODE_HWSS_RE EQADC_CFCR_MODE(5)
-#define EQADC_CFCR_MODE_HWSS_BE EQADC_CFCR_MODE(6)
-#define EQADC_CFCR_MODE_SWCS EQADC_CFCR_MODE(9)
-#define EQADC_CFCR_MODE_HWCS_LL EQADC_CFCR_MODE(10)
-#define EQADC_CFCR_MODE_HWCS_HL EQADC_CFCR_MODE(11)
-#define EQADC_CFCR_MODE_HWCS_FE EQADC_CFCR_MODE(12)
-#define EQADC_CFCR_MODE_HWCS_RE EQADC_CFCR_MODE(13)
-#define EQADC_CFCR_MODE_HWCS_BE EQADC_CFCR_MODE(14)
-#define EQADC_CFCR_AMODE0_MASK (15U << 0)
-#define EQADC_CFCR_AMODE0(n) ((n) << 0)
-/** @} */
-
-/**
- * @name EQADC FISR registers definitions
- * @{
- */
-#define EQADC_FISR_POPNXTPTR_MASK (15U << 0)
-#define EQADC_FISR_RFCTR_MASK (15U << 4)
-#define EQADC_FISR_TNXTPTR_MASK (15U << 8)
-#define EQADC_FISR_CFCTR_MASK (15U << 12)
-#define EQADC_FISR_RFDF (1U << 17)
-#define EQADC_FISR_RFOF (1U << 19)
-#define EQADC_FISR_CFFF (1U << 25)
-#define EQADC_FISR_SSS (1U << 26)
-#define EQADC_FISR_CFUF (1U << 27)
-#define EQADC_FISR_EOQF (1U << 28)
-#define EQADC_FISR_PF (1U << 29)
-#define EQADC_FISR_TORF (1U << 30)
-#define EQADC_FISR_NCF (1U << 31)
-#define EQADC_FISR_CLEAR_MASK (EQADC_FISR_NCF | EQADC_FISR_TORF | \
- EQADC_FISR_PF | EQADC_FISR_EOQF | \
- EQADC_FISR_CFUF | EQADC_FISR_RFOF | \
- EQADC_FISR_RFDF)
-/** @} */
-
-/**
- * @name EQADC conversion/configuration commands
- * @{
- */
-#define EQADC_CONV_CONFIG_STD (0U << 0) /**< @brief Alt.config.1. */
-#define EQADC_CONV_CONFIG_SEL1 (8U << 0) /**< @brief Alt.config.1. */
-#define EQADC_CONV_CONFIG_SEL2 (9U << 0) /**< @brief Alt.config.2. */
-#define EQADC_CONV_CONFIG_SEL3 (10U << 0) /**< @brief Alt.config.3. */
-#define EQADC_CONV_CONFIG_SEL4 (11U << 0) /**< @brief Alt.config.4. */
-#define EQADC_CONV_CONFIG_SEL5 (12U << 0) /**< @brief Alt.config.5. */
-#define EQADC_CONV_CONFIG_SEL6 (13U << 0) /**< @brief Alt.config.6. */
-#define EQADC_CONV_CONFIG_SEL7 (14U << 0) /**< @brief Alt.config.7. */
-#define EQADC_CONV_CONFIG_SEL8 (15U << 0) /**< @brief Alt.config.8. */
-#define EQADC_CONV_CHANNEL_MASK (255U << 8) /**< @brief Channel number mask.*/
-#define EQADC_CONV_CHANNEL(n) ((n) << 8) /**< @brief Channel number. */
-#define EQADC_CONV_FMT_RJU (0U << 16) /**< @brief Unsigned samples. */
-#define EQADC_CONV_FMT_RJS (1U << 16) /**< @brief Signed samples. */
-#define EQADC_CONV_TSR (1U << 17) /**< @brief Time stamp request. */
-#define EQADC_CONV_LST_MASK (3U << 18) /**< @brief Sample time. */
-#define EQADC_CONV_LST_2 (0U << 18) /**< @brief 2 clock cycles. */
-#define EQADC_CONV_LST_8 (1U << 18) /**< @brief 8 clock cycles. */
-#define EQADC_CONV_LST_64 (2U << 18) /**< @brief 64 clock cycles. */
-#define EQADC_CONV_LST_128 (3U << 18) /**< @brief 128 clock cycles. */
-#define EQADC_CONV_MSG_MASK (15U << 20) /**< @brief Message mask. */
-#define EQADC_CONV_MSG_RFIFO(n) ((n) << 20) /**< @brief Result in RFIFO0..5.*/
-#define EQADC_CONV_MSG_NULL (6U << 20) /**< @brief Null message. */
-#define EQADC_CONV_CAL (1U << 24) /**< @brief Calibrated result. */
-#define EQADC_CONV_BN_MASK (1U << 25) /**< @brief Buffer number mask. */
-#define EQADC_CONV_BN_ADC0 (0U << 25) /**< @brief ADC0 selection. */
-#define EQADC_CONV_BN_ADC1 (1U << 25) /**< @brief ADC1 selection. */
-#define EQADC_CONV_REP (1U << 29) /**< @brief Repeat loop flag. */
-#define EQADC_CONV_PAUSE (1U << 30) /**< @brief Pause flag. */
-#define EQADC_CONV_EOQ (1U << 31) /**< @brief End of queue flag. */
-/** @} */
-
-/**
- * @name EQADC read/write commands
- * @{
- */
-#define EQADC_RW_REG_ADDR_MASK (255U << 0)
-#define EQADC_RW_REG_ADDR(n) ((n) << 0)
-#define EQADC_RW_VALUE_MASK (0xFFFF << 8)
-#define EQADC_RW_VALUE(n) ((n) << 8)
-#define EQADC_RW_WRITE (0U << 24)
-#define EQADC_RW_READ (1U << 24)
-#define EQADC_RW_BN_ADC0 (0U << 25)
-#define EQADC_RW_BN_ADC1 (1U << 25)
-#define EQADC_RW_REP (1U << 29)
-#define EQADC_RW_PAUSE (1U << 30)
-#define EQADC_RW_EOQ (1U << 31)
-/** @} */
-
-/**
- * @name ADC CR register definitions
- * @{
- */
-#define ADC_CR_CLK_PS_MASK (31U << 0)
-#define ADC_CR_CLK_PS(n) ((((n) >> 1) - 1) | ((n) & 1 ? ADC_CR_ODD_PS\
- : 0))
-#define ADC_CR_CLK_SEL (1U << 5)
-#define ADC_CR_CLK_DTY (1U << 6)
-#define ADC_CR_ODD_PS (1U << 7)
-#define ADC_CR_TBSEL_MASK (3U << 8)
-#define ADC_CR_TBSEL(n) ((n) << 8)
-#define ADC_CR_EMUX (1U << 11)
-#define ADC_CR_EN (1U << 15)
-/** @} */
-
-/**
- * @name ADC AxCR registers definitions
- * @{
- */
-#define ADC_ACR_PRE_GAIN_MASK (3U << 0)
-#define ADC_ACR_PRE_GAIN_X1 (0U << 0)
-#define ADC_ACR_PRE_GAIN_X2 (1U << 0)
-#define ADC_ACR_PRE_GAIN_X4 (2U << 0)
-#define ADC_ACR_RESSEL_MASK (3U << 6)
-#define ADC_ACR_RESSEL_12BITS (0U << 6)
-#define ADC_ACR_RESSEL_10BITS (1U << 6)
-#define ADC_ACR_RESSEL_8BITS (2U << 6)
-/** @} */
-
-/**
- * @name ADC PUDCRx registers definitions
- * @{
- */
-#define ADC_PUDCR_NONE 0x0000
-#define ADC_PUDCR_UP_200K 0x1100
-#define ADC_PUDCR_UP_100K 0x1200
-#define ADC_PUDCR_UP_5K 0x1300
-#define ADC_PUDCR_DOWN_200K 0x2100
-#define ADC_PUDCR_DOWN_100K 0x2200
-#define ADC_PUDCR_DOWN_5K 0x2300
-#define ADC_PUDCR_UP_DOWN_200K 0x3100
-#define ADC_PUDCR_UP_DOWN_100K 0x3200
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ADCD1 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q0) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q0 FALSE
-#endif
-
-/**
- * @brief ADCD2 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q1) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q1 FALSE
-#endif
-
-/**
- * @brief ADCD3 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q2) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q2 FALSE
-#endif
-
-/**
- * @brief ADCD4 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q3) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q3 FALSE
-#endif
-
-/**
- * @brief ADCD5 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q4) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q4 FALSE
-#endif
-
-/**
- * @brief ADCD6 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q5) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q5 FALSE
-#endif
-
-/**
- * @brief EQADC CFIFO0 and RFIFO0 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC CFIFO1 and RFIFO1 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC CFIFO2 and RFIFO2 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC CFIFO3 and RFIFO3 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC CFIFO4 and RFIFO4 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC CFIFO5 and RFIFO5 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO5_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12
-#endif
-
-/**
- * @brief EQADC clock prescaler value.
- */
-#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__)
-#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
-#endif
-
-/**
- * @brief Initialization value for PUDCRx registers.
- */
-#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__)
-#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE, \
- ADC_PUDCR_NONE}
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EQADC
-#error "EQADC not present in the selected device"
-#endif
-
-#define SPC5_ADC_USE_ADC0 (SPC5_ADC_USE_ADC0_Q0 || \
- SPC5_ADC_USE_ADC0_Q1 || \
- SPC5_ADC_USE_ADC0_Q2)
-#define SPC5_ADC_USE_ADC1 (SPC5_ADC_USE_ADC1_Q3 || \
- SPC5_ADC_USE_ADC1_Q4 || \
- SPC5_ADC_USE_ADC1_Q5)
-
-#if !SPC5_ADC_USE_ADC0 && !SPC5_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*!
- * @brief FIFO unit numeric IDs.
- */
-typedef enum {
- ADC_FIFO_0 = 0,
- ADC_FIFO_1 = 1,
- ADC_FIFO_2 = 2,
- ADC_FIFO_3 = 3,
- ADC_FIFO_4 = 4,
- ADC_FIFO_5 = 5
-} adcfifo_t;
-
-/**
- * @brief ADC command data type.
- */
-typedef uint32_t adccommand_t;
-
-/**
- * @brief ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief Possible ADC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */
-} adcerror_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool_t circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief Initialization value for CFCR register.
- */
- uint16_t cfcr;
- /**
- * @brief SIU ETISR.TSEL value for this queue;
- */
- uint8_t tsel;
- /**
- * @brief SIU ISEL3.ETSEL value for this queue;
- */
- uint8_t etsel;
- /**
- * @brief Number of command iterations stored in @p commands.
- * @note The total number of array elements must be @p num_channels *
- * @p num_iterations.
- * @note This fields is the upper limit of the parameter @p n that can
- * be passed to the functions @p adcConvert() and
- * @p adcStartConversion().
- */
- uint32_t num_iterations;
- /**
- * @brief Pointer to an array of low level EQADC commands to be pushed
- * into the CFIFO during a conversion.
- */
- const adccommand_t *commands;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note Empty in this implementation can be ignored.
- */
-typedef struct {
- uint32_t dummy;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- Thread *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief CFIFO/RFIFO used by this instance.
- */
- adcfifo_t fifo;
- /**
- * @brief EDMA channel used for the CFIFO.
- */
- edma_channel_t cfifo_channel;
- /**
- * @brief EDMA channel used for the RFIFO.
- */
- edma_channel_t rfifo_channel;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_ADC_USE_ADC0_Q0 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if SPC5_ADC_USE_ADC0_Q1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD2;
-#endif
-
-#if SPC5_ADC_USE_ADC0_Q2 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD4;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q4 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD5;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q5 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c deleted file mode 100644 index 3257927c6..000000000 --- a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c +++ /dev/null @@ -1,296 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/ESCI_v1/serial_lld.c
- * @brief SPC5xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief eSCI-A serial driver identifier.
- */
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief eSCI-B serial driver identifier.
- */
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- SERIAL_DEFAULT_BITRATE,
- SD_MODE_NORMAL | SD_MODE_PARITY_NONE
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief eSCI initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration
- */
-static void esci_init(SerialDriver *sdp, const SerialConfig *config) {
- volatile struct ESCI_tag *escip = sdp->escip;
- uint8_t mode = config->sc_mode;
-
- escip->CR2.R = 0; /* MDIS off. */
- escip->CR1.R = 0;
- escip->LCR.R = 0;
- escip->CR1.B.SBR = SPC5_SYSCLK / (16 * config->sc_speed);
- if (mode & SD_MODE_LOOPBACK)
- escip->CR1.B.LOOPS = 1;
- switch (mode & SD_MODE_PARITY_MASK) {
- case SD_MODE_PARITY_ODD:
- escip->CR1.B.PT = 1;
- case SD_MODE_PARITY_EVEN:
- escip->CR1.B.PE = 1;
- escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */
- default:
- ;
- }
- escip->LPR.R = 0;
- escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */
- escip->CR2.R = 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */
-}
-
-/**
- * @brief eSCI de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] escip pointer to an eSCI I/O block
- */
-static void esci_deinit(volatile struct ESCI_tag *escip) {
-
- escip->LPR.R = 0;
- escip->SR.R = 0xFFFFFFFF;
- escip->CR1.R = 0;
- escip->CR2.R = 0x8000; /* MDIS on. */
-}
-
-/**
- * @brief Error handling routine.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] sr eSCI SR register value
- */
-static void set_error(SerialDriver *sdp, uint32_t sr) {
- flagsmask_t sts = 0;
-
- if (sr & 0x08000000)
- sts |= SD_OVERRUN_ERROR;
- if (sr & 0x04000000)
- sts |= SD_NOISE_ERROR;
- if (sr & 0x02000000)
- sts |= SD_FRAMING_ERROR;
- if (sr & 0x01000000)
- sts |= SD_PARITY_ERROR;
-/* if (sr & 0x00000000)
- sts |= SD_BREAK_DETECTED;*/
- chSysLockFromIsr();
- chnAddFlagsI(sdp, sts);
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Common IRQ handler.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-static void serve_interrupt(SerialDriver *sdp) {
- volatile struct ESCI_tag *escip = sdp->escip;
-
- uint32_t sr = escip->SR.R;
- escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/
- if (sr & 0x0F000000) /* OR | NF | FE | PF. */
- set_error(sdp, sr);
- if (sr & 0x20000000) { /* RDRF. */
- chSysLockFromIsr();
- sdIncomingDataI(sdp, escip->DR.B.D);
- chSysUnlockFromIsr();
- }
- if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */
- msg_t b;
- chSysLockFromIsr();
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- escip->CR1.B.TIE = 0;
- }
- else {
- ESCI_A.SR.B.TDRE = 1;
- escip->DR.R = (uint16_t)b;
- }
- chSysUnlockFromIsr();
- }
-}
-
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
- (void)qp;
- if (ESCI_A.SR.B.TDRE) {
- msg_t b = sdRequestDataI(&SD1);
- if (b != Q_EMPTY) {
- ESCI_A.SR.B.TDRE = 1;
- ESCI_A.CR1.B.TIE = 1;
- ESCI_A.DR.R = (uint16_t)b;
- }
- }
-}
-#endif
-
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
- (void)qp;
- if (ESCI_B.SR.B.TDRE) {
- msg_t b = sdRequestDataI(&SD2);
- if (b != Q_EMPTY) {
- ESCI_B.SR.B.TDRE = 1;
- ESCI_B.CR1.B.TIE = 1;
- ESCI_B.DR.R = (uint16_t)b;
- }
- }
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-#if !defined(SPC5_ESCIA_HANDLER)
-#error "SPC5_ESCIA_HANDLER not defined"
-#endif
-/**
- * @brief eSCI-A interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ESCIA_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-#if !defined(SPC5_ESCIB_HANDLER)
-#error "SPC5_ESCIB_HANDLER not defined"
-#endif
-/**
- * @brief eSCI-B interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ESCIB_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt(&SD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if SPC5_USE_ESCIA
- sdObjectInit(&SD1, NULL, notify1);
- SD1.escip = &ESCI_A;
- ESCI_A.CR2.R = 0x8000; /* MDIS ON. */
- INTC.PSR[SPC5_ESCIA_NUMBER].R = SPC5_ESCIA_PRIORITY;
-#endif
-
-#if SPC5_USE_ESCIB
- sdObjectInit(&SD2, NULL, notify2);
- SD2.escip = &ESCI_B;
- ESCI_B.CR2.R = 0x8000; /* MDIS ON. */
- INTC.PSR[SPC5_ESCIB_NUMBER].R = SPC5_ESCIB_PRIORITY;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
- esci_init(sdp, config);
-}
-
-/**
- * @brief Low level serial driver stop.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY)
- esci_deinit(sdp->escip);
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h deleted file mode 100644 index b8b29fb99..000000000 --- a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h +++ /dev/null @@ -1,170 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/ESCI_v1/serial_lld.c
- * @brief SPC5xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Serial port modes
- * @{
- */
-#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */
-#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */
-#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */
-#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */
-
-#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */
-#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief eSCI-A driver enable switch.
- * @details If set to @p TRUE the support for eSCI-A is included.
- * @note The default is @p TRUE.
- */
-#if !defined(SPC5_USE_ESCIA) || defined(__DOXYGEN__)
-#define SPC5_USE_ESCIA TRUE
-#endif
-
-/**
- * @brief eSCI-B driver enable switch.
- * @details If set to @p TRUE the support for eSCI-B is included.
- * @note The default is @p TRUE.
- */
-#if !defined(SPC5_USE_ESCIB) || defined(__DOXYGEN__)
-#define SPC5_USE_ESCIB TRUE
-#endif
-
-/**
- * @brief eSCI-A interrupt priority level setting.
- */
-#if !defined(SPC_ESCIA_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ESCIA_PRIORITY 8
-#endif
-
-/**
- * @brief eSCI-B interrupt priority level setting.
- */
-#if !defined(SPC_ESCIB_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ESCIB_PRIORITY 8
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA && !SPC5_HAS_ESCIA
-#error "eSCI-A not present in the selected device"
-#endif
-
-#if SPC5_USE_ESCIB && !SPC5_HAS_ESCIB
-#error "eSCI-B not present in the selected device"
-#endif
-
-#if !SPC5_USE_ESCIA && !SPC5_USE_ESCIB
-#error "SERIAL driver activated but no eSCI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note This structure content is architecture dependent, each driver
- * implementation defines its own version and the custom static
- * initializers.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t sc_speed;
- /**
- * @brief Mode flags.
- */
- uint8_t sc_mode;
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- InputQueue iqueue; \
- /* Output queue.*/ \
- OutputQueue oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the volatile eSCI registers block.*/ \
- volatile struct ESCI_tag *escip;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if SPC5_USE_ESCIB && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c deleted file mode 100644 index b20cc1334..000000000 --- a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c +++ /dev/null @@ -1,1667 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file FlexCAN_v1/can_lld.c
- * @brief SPC5xx CAN subsystem low level driver source.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief CAN1 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
-CANDriver CAND1;
-#endif
-
-/** @brief CAN2 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
-CANDriver CAND2;
-#endif
-
-/** @brief CAN3 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
-CANDriver CAND3;
-#endif
-
-/** @brief CAN4 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
-CANDriver CAND4;
-#endif
-
-/** @brief CAN5 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
-CANDriver CAND5;
-#endif
-
-/** @brief CAN6 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
-CANDriver CAND6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Common TX ISR handler.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_tx_handler(CANDriver *canp) {
- uint32_t iflag1, iflag2;
-
- iflag1 = canp->flexcan->IFRL.R;
- iflag2 = canp->flexcan->IFRH.R;
- /* No more events until a message is transmitted.*/
- canp->flexcan->IFRL.R |= iflag1 & 0xFFFFFF00;
- canp->flexcan->IFRH.R |= canp->flexcan->IFRH.R & 0xFFFFFFFF;
- chSysLockFromIsr();
- while (chSemGetCounterI(&canp->txsem) < 0)
- chSemSignalI(&canp->txsem);
-
-#if SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 32)
- if(&CAND1 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 64)
- if(&CAND1 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 32)
- if(&CAND2 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 64)
- if(&CAND2 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 32)
- if(&CAND3 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 64)
- if(&CAND3 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 32)
- if(&CAND4 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 64)
- if(&CAND4 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 32)
- if(&CAND5 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 64)
- if(&CAND5 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 32)
- if(&CAND6 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
- }
-#elif SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 64)
- if(&CAND6 == canp) {
- chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
- }
-#endif
-
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Common RX ISR handler.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_rx_handler(CANDriver *canp) {
- uint32_t iflag1;
-
- iflag1 = canp->flexcan->IFRL.R;
- if ((iflag1 & 0x000000FF) != 0) {
- chSysLockFromIsr();
- while (chSemGetCounterI(&canp->rxsem) < 0)
- chSemSignalI(&canp->rxsem);
- chEvtBroadcastFlagsI(&canp->rxfull_event, iflag1 & 0x000000FF);
- chSysUnlockFromIsr();
-
- /* Release the mailbox.*/
- canp->flexcan->IFRL.R |= iflag1 & 0x000000FF;
- }
-}
-
-/**
- * @brief Common error ISR handler.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_err_handler(CANDriver *canp) {
-
- uint32_t esr = canp->flexcan->ESR.R;
- flagsmask_t flags = 0;
-
- /* Error event.*/
- if ((esr & CAN_ESR_TWRN_INT) || (esr & CAN_ESR_RWRN_INT)) {
- canp->flexcan->ESR.B.TXWRN = 1U;
- canp->flexcan->ESR.B.RXWRN = 1U;
- flags |= CAN_LIMIT_WARNING;
- }
-
- if (esr & CAN_ESR_BOFF_INT) {
- canp->flexcan->ESR.B.BOFFINT = 1U;
- flags |= CAN_BUS_OFF_ERROR;
- }
-
- if (esr & CAN_ESR_ERR_INT) {
- canp->flexcan->ESR.B.ERRINT = 1U;
- flags |= CAN_FRAMING_ERROR;
- }
- chSysLockFromIsr();
- chEvtBroadcastFlagsI(&canp->error_event, flags);
- chSysUnlockFromIsr();
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
-/**
- * @brief CAN1 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER) {
-
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN1 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN1 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN0_MB == 64)
-/**
- * @brief CAN1 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN1 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN1 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN0 */
-
-#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
-/**
- * @brief CAN2 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN2 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN2 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN1_MB == 64)
-/**
- * @brief CAN2 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN2 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN2 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN2 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN2 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN1 */
-
-#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
-/**
- * @brief CAN3 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN3 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN3 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN2_MB == 64)
-/**
- * @brief CAN3 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN3 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN3 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN3 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN3 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN2 */
-
-#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
-/**
- * @brief CAN4 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN4 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN4 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN3_MB == 64)
-/**
- * @brief CAN4 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN4 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN4 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN4 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN4 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN3 */
-
-#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
-/**
- * @brief CAN5 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN5 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN5 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN4_MB == 64)
-/**
- * @brief CAN5 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN5 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN5 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN5 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN5 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN4 */
-
-#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
-/**
- * @brief CAN6 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN6 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN6 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN5_MB == 64)
-/**
- * @brief CAN6 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_tx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief CAN6 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief CAN6 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_rx_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN6 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief CAN6 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- can_lld_err_handler(&CAND6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_CAN_USE_FLEXCAN5 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-
-#if SPC5_CAN_USE_FLEXCAN0
- /* Driver initialization.*/
- canObjectInit(&CAND1);
- CAND1.flexcan = &SPC5_FLEXCAN_0;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1
- /* Driver initialization.*/
- canObjectInit(&CAND2);
- CAND2.flexcan = &SPC5_FLEXCAN_1;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2
- /* Driver initialization.*/
- canObjectInit(&CAND3);
- CAND3.flexcan = &SPC5_FLEXCAN_2;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3
- /* Driver initialization.*/
- canObjectInit(&CAND4);
- CAND4.flexcan = &SPC5_FLEXCAN_3;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4
- /* Driver initialization.*/
- canObjectInit(&CAND5);
- CAND5.flexcan = &SPC5_FLEXCAN_4;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5
- /* Driver initialization.*/
- canObjectInit(&CAND6);
- CAND6.flexcan = &SPC5_FLEXCAN_5;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
- INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R =
- SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-#endif
-}
-
-/**
- * @brief Configures and activates the CAN peripheral.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_start(CANDriver *canp) {
-
- uint8_t mb_index = 0, id = 0;
-
- /* Clock activation.*/
-#if SPC5_CAN_USE_FLEXCAN0
- /* Set peripheral clock mode.*/
- if(&CAND1 == canp)
- SPC5_FLEXCAN0_ENABLE_CLOCK();
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1
- /* Set peripheral clock mode.*/
- if(&CAND2 == canp)
- SPC5_FLEXCAN1_ENABLE_CLOCK();
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2
- /* Set peripheral clock mode.*/
- if(&CAND3 == canp)
- SPC5_FLEXCAN2_ENABLE_CLOCK();
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3
- /* Set peripheral clock mode.*/
- if(&CAND4 == canp)
- SPC5_FLEXCAN3_ENABLE_CLOCK();
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4
- /* Set peripheral clock mode.*/
- if(&CAND5 == canp)
- SPC5_FLEXCAN4_ENABLE_CLOCK();
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5
- /* Set peripheral clock mode.*/
- if(&CAND6 == canp)
- SPC5_FLEXCAN5_ENABLE_CLOCK();
-#endif
-
- /* Entering initialization mode. */
- canp->state = CAN_STARTING;
- canp->flexcan->CR.R |= CAN_CTRL_CLK_SRC;
- canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
-
- /*
- * Individual filtering per MB, disable frame self reception,
- * disable the FIFO, enable SuperVisor mode.
- */
-#if SPC5_CAN_USE_FLEXCAN0
- if(&CAND1 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN0_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1
- if(&CAND2 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN1_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2
- if(&CAND3 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN2_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3
- if(&CAND4 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN3_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4
- if(&CAND5 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN4_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5
- if(&CAND6 == canp)
- canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN5_MB - 1);
-#endif
-
- canp->flexcan->CR.R |= CAN_CTRL_TSYN | CAN_CTRL_RJW(3);
-
- /* TX MB initialization.*/
-#if SPC5_CAN_USE_FLEXCAN0
- if(&CAND1 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN0_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
- if(&CAND2 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN1_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
- if(&CAND3 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN2_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
- if(&CAND4 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN3_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
- if(&CAND5 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN4_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
- if(&CAND6 == canp) {
- for(mb_index = 0; mb_index < (SPC5_FLEXCAN5_MB - CAN_RX_MAILBOXES);
- mb_index++) {
- canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
- }
- }
-#endif
-
- /* Unlock Message buffers.*/
- (void) canp->flexcan->TIMER.R;
-
- /* MCR initialization.*/
- canp->flexcan->MCR.R |= canp->config->mcr;
-
- /* CTRL initialization.*/
- canp->flexcan->CR.R |= canp->config->ctrl;
-
- /* Interrupt sources initialization.*/
- canp->flexcan->MCR.R |= CAN_MCR_WRN_EN;
-
- canp->flexcan->CR.R |= CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK |
- CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK;
-
-#if !SPC5_CAN_USE_FILTERS
- /* RX MB initialization.*/
- for(mb_index = 0; mb_index < CAN_RX_MAILBOXES; mb_index++) {
- canp->flexcan->BUF[mb_index].CS.B.CODE = 0U;
- if(mb_index < 4) {
- canp->flexcan->BUF[mb_index].CS.B.IDE = 0U;
- }
- else {
- canp->flexcan->BUF[mb_index].CS.B.IDE = 1U;
- }
- canp->flexcan->BUF[mb_index].ID.R = 0U;
- canp->flexcan->BUF[mb_index].CS.B.CODE = 4U;
- }
-
- /* Receive all.*/
- canp->flexcan->RXGMASK.R = 0x00000000;
-#else
- for (id = 0; id < CAN_RX_MAILBOXES; id++) {
- canp->flexcan->BUF[id].CS.B.CODE = 0U;
- if (canp->config->RxFilter[id].scale) {
- canp->flexcan->BUF[id].CS.B.IDE = 1U;
- canp->flexcan->BUF[id].ID.R = canp->config->RxFilter[id].register1;
- }
- else {
- canp->flexcan->BUF[id].CS.B.IDE = 0U;
- canp->flexcan->BUF[id].ID.B.STD_ID = canp->config->RxFilter[id].register1;
- canp->flexcan->BUF[id].ID.B.EXT_ID = 0U;
- }
- /* RX MB initialization.*/
- canp->flexcan->BUF[id].CS.B.CODE = 4U;
- }
- canp->flexcan->RXGMASK.R = 0x0FFFFFFF;
-#endif
-
- /* Enable MBs interrupts.*/
-#if SPC5_CAN_USE_FLEXCAN0
- if(&CAND1 == canp) {
- if(SPC5_FLEXCAN0_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN0_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
- if(&CAND2 == canp) {
- if(SPC5_FLEXCAN1_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN1_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
- if(&CAND3 == canp) {
- if(SPC5_FLEXCAN2_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN2_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
- if(&CAND4 == canp) {
- if(SPC5_FLEXCAN3_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN3_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
- if(&CAND5 == canp) {
- if(SPC5_FLEXCAN4_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN4_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
- if(&CAND6 == canp) {
- if(SPC5_FLEXCAN5_MB == 32) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- }
- else if(SPC5_FLEXCAN5_MB == 64) {
- canp->flexcan->IMRL.R = 0xFFFFFFFF;
- canp->flexcan->IMRH.R = 0xFFFFFFFF;
- }
- }
-#endif
-
- /* CAN BUS synchronization.*/
- canp->flexcan->MCR.B.HALT = 0;
-}
-
-/**
- * @brief Deactivates the CAN peripheral.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
- /* If in ready state then disables the CAN peripheral.*/
- if (canp->state == CAN_READY) {
-
- /* Disable Interrupt sources.*/
- canp->flexcan->MCR.R &= ~CAN_MCR_WRN_EN;
- canp->flexcan->CR.R &= ~(CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK |
- CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK);
- canp->flexcan->IMRL.R = 0x00000000;
-
- canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
-
-#if SPC5_CAN_USE_FLEXCAN0
- /* Set peripheral clock mode.*/
- if(&CAND1 == canp)
- SPC5_FLEXCAN0_DISABLE_CLOCK();
-
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
- /* Set peripheral clock mode.*/
- if(&CAND2 == canp)
- SPC5_FLEXCAN1_DISABLE_CLOCK();
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
- /* Set peripheral clock mode.*/
- if(&CAND3 == canp)
- SPC5_FLEXCAN2_DISABLE_CLOCK();
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
- /* Set peripheral clock mode.*/
- if(&CAND4 == canp)
- SPC5_FLEXCAN3_DISABLE_CLOCK();
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
- /* Set peripheral clock mode.*/
- if(&CAND5 == canp)
- SPC5_FLEXCAN4_DISABLE_CLOCK();
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
- /* Set peripheral clock mode.*/
- if(&CAND6 == canp)
- SPC5_FLEXCAN5_DISABLE_CLOCK();
-#endif
- }
-}
-
-/**
- * @brief Determines whether a frame can be transmitted.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return The queue space availability.
- * @retval FALSE no space in the transmit queue.
- * @retval TRUE transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
- uint8_t mbid = 0;
-
- if(mailbox == CAN_ANY_MAILBOX) {
-#if SPC5_CAN_USE_FLEXCAN0
- if(&CAND1 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
- if(&CAND2 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
- if(&CAND3 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
- if(&CAND4 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
- if(&CAND5 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
- if(&CAND6 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
- if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
- return TRUE;
- }
- }
- return FALSE;
- }
-#endif
- }
- else {
- return canp->flexcan->BUF[mailbox + 7].CS.B.CODE == 0x08;
- }
- return FALSE;
-}
-
-/**
- * @brief Inserts a frame into the transmit queue.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] ctfp pointer to the CAN frame to be transmitted
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp,
- canmbx_t mailbox,
- const CANTxFrame *ctfp) {
-
- CAN_TxMailBox_TypeDef *tmbp = NULL;
- uint8_t mbid = 0;
-
- /* Pointer to a free transmission mailbox.*/
- if (mailbox == CAN_ANY_MAILBOX) {
-#if SPC5_CAN_USE_FLEXCAN0
- if(&CAND1 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
- if(&CAND2 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
- if(&CAND3 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
- if(&CAND4 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
- if(&CAND5 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
- if(&CAND6 == canp) {
- for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
- if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
- break;
- }
- }
- }
-#endif
- }
- else {
- tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mailbox + 7];
- }
-
- /* Preparing the message.*/
- if (ctfp->IDE) {
- tmbp->CS.B.IDE = 1U;
- tmbp->CS.B.RTR = 0U;
- tmbp->ID.R = ctfp->EID;
- }
- else {
- tmbp->CS.B.IDE = 0U;
- tmbp->CS.B.RTR = 0U;
- tmbp->ID.R = ctfp->SID << 18;
- }
- tmbp->CS.B.LENGTH = ctfp->LENGTH;
- tmbp->DATA[0] = ctfp->data32[0];
- tmbp->DATA[1] = ctfp->data32[1];
- tmbp->CS.B.CODE = 0x0C;
-}
-
-/**
- *
- * @brief Determines whether a frame has been received.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return The queue space availability.
- * @retval FALSE no space in the transmit queue.
- * @retval TRUE transmit slot available.
- *
- * @notapi
- */
-
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
- uint8_t mbid = 0;
- bool_t mb_status = FALSE;
-
- switch (mailbox) {
- case CAN_ANY_MAILBOX:
- for (mbid = 0; mbid < CAN_RX_MAILBOXES; mbid++) {
- if(canp->flexcan->BUF[mbid].CS.B.CODE == 2U) {
- mb_status = TRUE;
- }
- }
- return mb_status;
- case 1:
- return (canp->flexcan->BUF[0].CS.B.CODE == 2U);
- case 2:
- return (canp->flexcan->BUF[1].CS.B.CODE == 2U);
- case 3:
- return (canp->flexcan->BUF[2].CS.B.CODE == 2U);
- case 4:
- return (canp->flexcan->BUF[3].CS.B.CODE == 2U);
- case 5:
- return (canp->flexcan->BUF[4].CS.B.CODE == 2U);
- case 6:
- return (canp->flexcan->BUF[5].CS.B.CODE == 2U);
- case 7:
- return (canp->flexcan->BUF[6].CS.B.CODE == 2U);
- case 8:
- return (canp->flexcan->BUF[7].CS.B.CODE == 2U);
- default:
- return FALSE;
- }
-}
-
-/**
- * @brief Receives a frame from the input queue.
- *
- * @param[in] canp pointer to the @p CANDriver object
- * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp,
- canmbx_t mailbox,
- CANRxFrame *crfp) {
-
- uint32_t mbid = 0, index = 0;
-
- if(mailbox != CAN_ANY_MAILBOX) {
- mbid = mailbox;
- }
- else {
- for (index = 0; index < CAN_RX_MAILBOXES; index++) {
- if(canp->flexcan->BUF[index].CS.B.CODE == 2U) {
- mbid = index;
- break;
- }
- }
- }
-
- /* Lock the RX MB.*/
- (void) canp->flexcan->BUF[mbid].CS.B.CODE;
-
- /* Fetches the message.*/
- crfp->data32[0] = canp->flexcan->BUF[mbid].DATA.W[0];
- crfp->data32[1] = canp->flexcan->BUF[mbid].DATA.W[1];
-
- /* Decodes the various fields in the RX frame.*/
- crfp->RTR = canp->flexcan->BUF[mbid].CS.B.RTR;
- crfp->IDE = canp->flexcan->BUF[mbid].CS.B.IDE;
- if (crfp->IDE)
- crfp->EID = canp->flexcan->BUF[mbid].ID.B.EXT_ID;
- else
- crfp->SID = canp->flexcan->BUF[mbid].ID.B.STD_ID;
- crfp->LENGTH = canp->flexcan->BUF[mbid].CS.B.LENGTH;
- crfp->TIME = canp->flexcan->BUF[mbid].CS.B.TIMESTAMP;
-
- /* Unlock the RX MB.*/
- (void) canp->flexcan->TIMER.R;
-
- /* Reconfigure the RX MB in empty status.*/
- canp->flexcan->BUF[mbid].CS.B.CODE = 4U;
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief Enters the sleep mode.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-
- /*canp->can->MCR |= CAN_MCR_SLEEP;*/
-}
-
-/**
- * @brief Enforces leaving the sleep mode.
- *
- * @param[in] canp pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-
- /*canp->can->MCR &= ~CAN_MCR_SLEEP;*/
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h deleted file mode 100644 index ad67c97da..000000000 --- a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h +++ /dev/null @@ -1,520 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file FlexCAN_v1/can_lld.h
- * @brief SPC5xx CAN subsystem low level driver header.
- *
- * @addtogroup CAN
- * @{
- */
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-#include "spc5_flexcan.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief This switch defines whether the driver implementation supports
- * a low power switch mode with an automatic wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP FALSE
-
-/**
- * @brief This implementation supports 24 transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES 24
-
-/**
- * @brief This implementation supports one FIFO receive mailbox.
- */
-#define CAN_RX_MAILBOXES 8
-
-/**
- * @brief This implementation supports eight FIFO receive filters.
- */
-#define SPC5_CAN_MAX_FILTERS 8
-
-/**
- * @brief Enable filters.
- */
-#define SPC5_CAN_FILTER_ON 1
-
-/**
- * @brief Disable filters.
- */
-#define SPC5_CAN_FILTER_OFF 0
-/**
- * @name CAN registers helper macros
- * @{
- */
-#define CAN_MCR_MAXMB(n) (n)
-#define CAN_MCR_AEN (1 << 12)
-#define CAN_MCR_LPRIO_EN (1 << 13)
-#define CAN_MCR_BCC (1 << 16)
-#define CAN_MCR_SRX_DIS (1 << 17)
-#define CAN_MCR_LPM_ACK (1 << 20)
-#define CAN_MCR_WRN_EN (1 << 21)
-#define CAN_MCR_SUPV (1 << 23)
-#define CAN_MCR_FRZ_ACK (1 << 24)
-#define CAN_MCR_WAK_MSK (1 << 26)
-#define CAN_MCR_NOT_RDY (1 << 27)
-#define CAN_MCR_HALT (1 << 28)
-#define CAN_MCR_FEN (1 << 29)
-#define CAN_MCR_FRZ (1 << 30)
-#define CAN_MCR_MDIS (1 << 31)
-
-#define CAN_CTRL_PROPSEG(n) (n)
-#define CAN_CTRL_LOM (1 << 3)
-#define CAN_CTRL_TSYN (1 << 5)
-#define CAN_CTRL_BOFF_REC (1 << 6)
-#define CAN_CTRL_SMP (1 << 7)
-#define CAN_CTRL_RWRN_MSK (1 << 10)
-#define CAN_CTRL_TWRN_MSK (1 << 11)
-#define CAN_CTRL_LPB (1 << 12)
-#define CAN_CTRL_CLK_SRC (1 << 13)
-#define CAN_CTRL_ERR_MSK (1 << 14)
-#define CAN_CTRL_BOFF_MSK (1 << 15)
-#define CAN_CTRL_PSEG2(n) ((n) << 16)
-#define CAN_CTRL_PSEG1(n) ((n) << 19)
-#define CAN_CTRL_RJW(n) ((n) << 22)
-#define CAN_CTRL_PRESDIV(n) ((n) << 24)
-
-#define CAN_IDE_STD 0 /**< @brief Standard id. */
-#define CAN_IDE_EXT 1 /**< @brief Extended id. */
-
-#define CAN_RTR_DATA 0 /**< @brief Data frame. */
-#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */
-
-#define CAN_ESR_ERR_INT (1 << 1)
-#define CAN_ESR_BOFF_INT (1 << 2)
-#define CAN_ESR_TWRN_INT (1 << 14)
-#define CAN_ESR_RWRN_INT (1 << 15)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief CAN1 driver enable switch.
- * @details If set to @p TRUE the support for CAN1 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN0) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN0 FALSE
-#endif
-
-/**
- * @brief CAN2 driver enable switch.
- * @details If set to @p TRUE the support for CAN2 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN1) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN1 FALSE
-#endif
-
-/**
- * @brief CAN3 driver enable switch.
- * @details If set to @p TRUE the support for CAN3 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN2) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN2 FALSE
-#endif
-
-/**
- * @brief CAN4 driver enable switch.
- * @details If set to @p TRUE the support for CAN4 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN3) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN3 FALSE
-#endif
-
-/**
- * @brief CAN5 driver enable switch.
- * @details If set to @p TRUE the support for CAN5 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN4) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN4 FALSE
-#endif
-
-/**
- * @brief CAN6 driver enable switch.
- * @details If set to @p TRUE the support for CAN6 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN5) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN5 FALSE
-#endif
-
-/**
- * @brief CAN1 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN2 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN3 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN4 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN3_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN5 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN4_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN6 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN5_IRQ_PRIORITY 11
-#endif
-/** @} */
-
-/**
- * @brief CAN filters enable setting.
- */
-#if !defined(SPC5_CAN_USE_FILTERS) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FILTERS FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 && !SPC5_HAS_FLEXCAN0
-#error "CAN1 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1 && !SPC5_HAS_FLEXCAN1
-#error "CAN2 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2 && !SPC5_HAS_FLEXCAN2
-#error "CAN3 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3 && !SPC5_HAS_FLEXCAN3
-#error "CAN4 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4 && !SPC5_HAS_FLEXCAN4
-#error "CAN5 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5 && !SPC5_HAS_FLEXCAN5
-#error "CAN6 not present in the selected device"
-#endif
-
-#if !SPC5_CAN_USE_FLEXCAN0 && !SPC5_CAN_USE_FLEXCAN1 \
- && !SPC5_CAN_USE_FLEXCAN2 && !SPC5_CAN_USE_FLEXCAN3 \
- && !SPC5_CAN_USE_FLEXCAN4 && !SPC5_CAN_USE_FLEXCAN5
-#error "CAN driver activated but no CAN peripheral assigned"
-#endif
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a transmission mailbox index.
- */
-typedef uint32_t canmbx_t;
-
-/**
- * @brief CAN TX MB structure.
- */
-typedef struct {
- union {
- vuint32_t R;
- struct {
- vuint8_t:4;
- vuint8_t CODE:4;
- vuint8_t:1;
- vuint8_t SRR:1;
- vuint8_t IDE:1;
- vuint8_t RTR:1;
- vuint8_t LENGTH:4;
- vuint16_t TIMESTAMP:16;
- } B;
- } CS;
-
- union {
- vuint32_t R;
- struct {
- vuint8_t PRIO:3;
- vuint32_t ID:29;
- } B;
- } ID;
- vuint32_t DATA[2]; /* Data buffer in words (32 bits) */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief CAN transmission frame.
- * @note Accessing the frame data as word16 or word32 is not portable because
- * machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
- struct {
- uint8_t LENGTH:4; /**< @brief Data length. */
- uint8_t RTR:1; /**< @brief Frame type. */
- uint8_t IDE:1; /**< @brief Identifier type. */
- };
- union {
- struct {
- uint32_t SID:11; /**< @brief Standard identifier.*/
- };
- struct {
- uint32_t EID:29; /**< @brief Extended identifier.*/
- };
- };
- union {
- uint8_t data8[8]; /**< @brief Frame data. */
- uint16_t data16[4]; /**< @brief Frame data. */
- uint32_t data32[2]; /**< @brief Frame data. */
- };
-} CANTxFrame;
-
-/**
- * @brief CAN received frame.
- * @note Accessing the frame data as word16 or word32 is not portable because
- * machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
- struct {
- uint16_t TIME; /**< @brief Time stamp. */
- };
- struct {
- uint8_t LENGTH:4; /**< @brief Data length. */
- uint8_t RTR:1; /**< @brief Frame type. */
- uint8_t IDE:1; /**< @brief Identifier type. */
- };
- union {
- struct {
- uint32_t SID:11; /**< @brief Standard identifier.*/
- };
- struct {
- uint32_t EID:29; /**< @brief Extended identifier.*/
- };
- };
- union {
- uint8_t data8[8]; /**< @brief Frame data. */
- uint16_t data16[4]; /**< @brief Frame data. */
- uint32_t data32[2]; /**< @brief Frame data. */
- };
-} CANRxFrame;
-
-/**
- * @brief CAN filter.
- * @note Refer to the SPC5 reference manual for info about filters.
- */
-typedef struct {
- /**
- * @brief Filter scale.
- * @note This bit represents the EXT bit associated to this
- * filter (0=standard ID mode, 1=extended ID mode).
- */
- uint32_t scale:1;
- /**
- * @brief Filter register (identifier).
- */
- uint32_t register1;
-} CANFilter;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief CAN MCR register initialization data.
- * @note Some bits in this register are enforced by the driver regardless
- * their status in this field.
- */
- uint32_t mcr;
- /**
- * @brief CAN CTRL register initialization data.
- * @note Some bits in this register are enforced by the driver regardless
- * their status in this field.
- */
- uint32_t ctrl;
-#if SPC5_CAN_USE_FILTERS
- /**
- * @brief CAN filters structure.
- */
- CANFilter RxFilter[CAN_RX_MAILBOXES];
-#endif
-} CANConfig;
-
-/**
- * @brief Structure representing an CAN driver.
- */
-typedef struct {
- /**
- * @brief Driver state.
- */
- canstate_t state;
- /**
- * @brief Current configuration data.
- */
- const CANConfig *config;
- /**
- * @brief Transmission queue semaphore.
- */
- Semaphore txsem;
- /**
- * @brief Receive queue semaphore.
- */
- Semaphore rxsem;
- /**
- * @brief One or more frames become available.
- * @note After broadcasting this event it will not be broadcasted again
- * until the received frames queue has been completely emptied. It
- * is <b>not</b> broadcasted for each received frame. It is
- * responsibility of the application to empty the queue by
- * repeatedly invoking @p chReceive() when listening to this event.
- * This behavior minimizes the interrupt served by the system
- * because CAN traffic.
- * @note The flags associated to the listeners will indicate which
- * receive mailboxes become non-empty.
- */
- EventSource rxfull_event;
- /**
- * @brief One or more transmission mailbox become available.
- * @note The flags associated to the listeners will indicate which
- * transmit mailboxes become empty.
- *
- */
- EventSource txempty_event;
- /**
- * @brief A CAN bus error happened.
- * @note The flags associated to the listeners will indicate the
- * error(s) that have occurred.
- */
- EventSource error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
- /**
- * @brief Entering sleep state event.
- */
- EventSource sleep_event;
- /**
- * @brief Exiting sleep state event.
- */
- EventSource wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the CAN registers.
- */
- volatile struct spc5_flexcan *flexcan;
-} CANDriver;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 && !defined(__DOXYGEN__)
-extern CANDriver CAND1;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1 && !defined(__DOXYGEN__)
-extern CANDriver CAND2;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2 && !defined(__DOXYGEN__)
-extern CANDriver CAND3;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3 && !defined(__DOXYGEN__)
-extern CANDriver CAND4;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4 && !defined(__DOXYGEN__)
-extern CANDriver CAND5;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5 && !defined(__DOXYGEN__)
-extern CANDriver CAND6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void can_lld_init(void);
- void can_lld_start(CANDriver *canp);
- void can_lld_stop(CANDriver *canp);
- bool_t can_lld_is_tx_empty(CANDriver *canp,
- canmbx_t mailbox);
- void can_lld_transmit(CANDriver *canp,
- canmbx_t mailbox,
- const CANTxFrame *crfp);
- bool_t can_lld_is_rx_nonempty(CANDriver *canp,
- canmbx_t mailbox);
- void can_lld_receive(CANDriver *canp,
- canmbx_t mailbox,
- CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
- void can_lld_sleep(CANDriver *canp);
- void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h deleted file mode 100644 index 580f78827..000000000 --- a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h +++ /dev/null @@ -1,442 +0,0 @@ -/*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file FlexCAN_v1/spc5_flexcan.h
- * @brief SPC5xx FlexCAN header file.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _SPC5_FLEXCAN_H_
-#define _SPC5_FLEXCAN_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief SPC5 FlexCAN registers block.
- * @note Redefined from the SPC5 headers because the non uniform
- * declaration of the SubModules registers among the various
- * sub-families.
- */
-struct FLEXCAN_BUFFER_t {
- union {
- vuint32_t R;
- struct {
- vuint32_t:4;
- vuint32_t CODE:4;
- vuint32_t:1;
- vuint32_t SRR:1;
- vuint32_t IDE:1;
- vuint32_t RTR:1;
- vuint32_t LENGTH:4;
- vuint32_t TIMESTAMP:16;
- } B;
- } CS;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t PRIO:3;
- vuint32_t STD_ID:11;
- vuint32_t EXT_ID:18;
- } B;
- } ID;
-
- union {
- /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
- /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
- vuint32_t W[2]; /* Data buffer in words (32 bits) */
- /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
- } DATA;
-
-}; /* end of FLEXCAN_BUF_t */
-
-struct FLEXCAN_RXFIFO_BUFFER_t {
- union {
- vuint32_t R;
- struct {
- vuint32_t:9;
- vuint32_t SRR:1;
- vuint32_t IDE:1;
- vuint32_t RTR:1;
- vuint32_t LENGTH:4;
- vuint32_t TIMESTAMP:16;
- } B;
- } CS;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t:3;
- vuint32_t STD_ID:11;
- vuint32_t EXT_ID:18;
- } B;
- } ID;
-
- union {
- /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
- /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
- vuint32_t W[2]; /* Data buffer in words (32 bits) */
- /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
- } DATA;
-
- uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
-
- union {
- vuint32_t R;
- } IDTABLE[8];
-
-}; /* end of FLEXCAN_RXFIFO_t */
-
-struct spc5_flexcan {
- union {
- vuint32_t R;
- struct {
- vuint32_t MDIS:1;
- vuint32_t FRZ:1;
- vuint32_t FEN:1;
- vuint32_t HALT:1;
- vuint32_t NOTRDY:1;
- vuint32_t WAKMSK:1;
- vuint32_t SOFTRST:1;
- vuint32_t FRZACK:1;
- vuint32_t SUPV:1;
- vuint32_t SLFWAK:1;
- vuint32_t WRNEN:1;
- vuint32_t LPMACK:1;
- vuint32_t WAKSRC:1;
- vuint32_t:1;
- vuint32_t SRXDIS:1;
- vuint32_t BCC:1;
- vuint32_t:2;
- vuint32_t LPRIO_EN:1;
- vuint32_t AEN:1;
- vuint32_t:2;
- vuint32_t IDAM:2;
- vuint32_t:2;
- vuint32_t MAXMB:6;
- } B;
- } MCR; /* Module Configuration Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t PRESDIV:8;
- vuint32_t RJW:2;
- vuint32_t PSEG1:3;
- vuint32_t PSEG2:3;
- vuint32_t BOFFMSK:1;
- vuint32_t ERRMSK:1;
- vuint32_t CLKSRC:1;
- vuint32_t LPB:1;
- vuint32_t TWRNMSK:1;
- vuint32_t RWRNMSK:1;
- vuint32_t:2;
- vuint32_t SMP:1;
- vuint32_t BOFFREC:1;
- vuint32_t TSYN:1;
- vuint32_t LBUF:1;
- vuint32_t LOM:1;
- vuint32_t PROPSEG:3;
- } B;
- } CR; /* Control Register */
-
- union {
- vuint32_t R;
- } TIMER; /* Free Running Timer */
-
- uint32_t FLEXCAN_reserved1;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MI:32;
- } B;
- } RXGMASK; /* RX Global Mask */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MI:32;
- } B;
- } RX14MASK; /* RX 14 Mask */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MI:32;
- } B;
- } RX15MASK; /* RX 15 Mask */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t:16;
- vuint32_t RXECNT:8;
- vuint32_t TXECNT:8;
- } B;
- } ECR; /* Error Counter Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t:14;
- vuint32_t TWRNINT:1;
- vuint32_t RWRNINT:1;
- vuint32_t BIT1ERR:1;
- vuint32_t BIT0ERR:1;
- vuint32_t ACKERR:1;
- vuint32_t CRCERR:1;
- vuint32_t FRMERR:1;
- vuint32_t STFERR:1;
- vuint32_t TXWRN:1;
- vuint32_t RXWRN:1;
- vuint32_t IDLE:1;
- vuint32_t TXRX:1;
- vuint32_t FLTCONF:2;
- vuint32_t:1;
- vuint32_t BOFFINT:1;
- vuint32_t ERRINT:1;
- vuint32_t WAKINT:1;
- } B;
- } ESR; /* Error and Status Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t BUF63M:1;
- vuint32_t BUF62M:1;
- vuint32_t BUF61M:1;
- vuint32_t BUF60M:1;
- vuint32_t BUF59M:1;
- vuint32_t BUF58M:1;
- vuint32_t BUF57M:1;
- vuint32_t BUF56M:1;
- vuint32_t BUF55M:1;
- vuint32_t BUF54M:1;
- vuint32_t BUF53M:1;
- vuint32_t BUF52M:1;
- vuint32_t BUF51M:1;
- vuint32_t BUF50M:1;
- vuint32_t BUF49M:1;
- vuint32_t BUF48M:1;
- vuint32_t BUF47M:1;
- vuint32_t BUF46M:1;
- vuint32_t BUF45M:1;
- vuint32_t BUF44M:1;
- vuint32_t BUF43M:1;
- vuint32_t BUF42M:1;
- vuint32_t BUF41M:1;
- vuint32_t BUF40M:1;
- vuint32_t BUF39M:1;
- vuint32_t BUF38M:1;
- vuint32_t BUF37M:1;
- vuint32_t BUF36M:1;
- vuint32_t BUF35M:1;
- vuint32_t BUF34M:1;
- vuint32_t BUF33M:1;
- vuint32_t BUF32M:1;
- } B;
- } IMRH; /* Interruput Masks Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t BUF31M:1;
- vuint32_t BUF30M:1;
- vuint32_t BUF29M:1;
- vuint32_t BUF28M:1;
- vuint32_t BUF27M:1;
- vuint32_t BUF26M:1;
- vuint32_t BUF25M:1;
- vuint32_t BUF24M:1;
- vuint32_t BUF23M:1;
- vuint32_t BUF22M:1;
- vuint32_t BUF21M:1;
- vuint32_t BUF20M:1;
- vuint32_t BUF19M:1;
- vuint32_t BUF18M:1;
- vuint32_t BUF17M:1;
- vuint32_t BUF16M:1;
- vuint32_t BUF15M:1;
- vuint32_t BUF14M:1;
- vuint32_t BUF13M:1;
- vuint32_t BUF12M:1;
- vuint32_t BUF11M:1;
- vuint32_t BUF10M:1;
- vuint32_t BUF09M:1;
- vuint32_t BUF08M:1;
- vuint32_t BUF07M:1;
- vuint32_t BUF06M:1;
- vuint32_t BUF05M:1;
- vuint32_t BUF04M:1;
- vuint32_t BUF03M:1;
- vuint32_t BUF02M:1;
- vuint32_t BUF01M:1;
- vuint32_t BUF00M:1;
- } B;
- } IMRL; /* Interruput Masks Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t BUF63I:1;
- vuint32_t BUF62I:1;
- vuint32_t BUF61I:1;
- vuint32_t BUF60I:1;
- vuint32_t BUF59I:1;
- vuint32_t BUF58I:1;
- vuint32_t BUF57I:1;
- vuint32_t BUF56I:1;
- vuint32_t BUF55I:1;
- vuint32_t BUF54I:1;
- vuint32_t BUF53I:1;
- vuint32_t BUF52I:1;
- vuint32_t BUF51I:1;
- vuint32_t BUF50I:1;
- vuint32_t BUF49I:1;
- vuint32_t BUF48I:1;
- vuint32_t BUF47I:1;
- vuint32_t BUF46I:1;
- vuint32_t BUF45I:1;
- vuint32_t BUF44I:1;
- vuint32_t BUF43I:1;
- vuint32_t BUF42I:1;
- vuint32_t BUF41I:1;
- vuint32_t BUF40I:1;
- vuint32_t BUF39I:1;
- vuint32_t BUF38I:1;
- vuint32_t BUF37I:1;
- vuint32_t BUF36I:1;
- vuint32_t BUF35I:1;
- vuint32_t BUF34I:1;
- vuint32_t BUF33I:1;
- vuint32_t BUF32I:1;
- } B;
- } IFRH; /* Interruput Flag Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t BUF31I:1;
- vuint32_t BUF30I:1;
- vuint32_t BUF29I:1;
- vuint32_t BUF28I:1;
- vuint32_t BUF27I:1;
- vuint32_t BUF26I:1;
- vuint32_t BUF25I:1;
- vuint32_t BUF24I:1;
- vuint32_t BUF23I:1;
- vuint32_t BUF22I:1;
- vuint32_t BUF21I:1;
- vuint32_t BUF20I:1;
- vuint32_t BUF19I:1;
- vuint32_t BUF18I:1;
- vuint32_t BUF17I:1;
- vuint32_t BUF16I:1;
- vuint32_t BUF15I:1;
- vuint32_t BUF14I:1;
- vuint32_t BUF13I:1;
- vuint32_t BUF12I:1;
- vuint32_t BUF11I:1;
- vuint32_t BUF10I:1;
- vuint32_t BUF09I:1;
- vuint32_t BUF08I:1;
- vuint32_t BUF07I:1;
- vuint32_t BUF06I:1;
- vuint32_t BUF05I:1;
- vuint32_t BUF04I:1;
- vuint32_t BUF03I:1;
- vuint32_t BUF02I:1;
- vuint32_t BUF01I:1;
- vuint32_t BUF00I:1;
- } B;
- } IFRL; /* Interruput Flag Register */
-
- uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
-/****************************************************************************/
- /* Standard Buffer Structure */
- struct FLEXCAN_BUFFER_t BUF[64];
-
- /* RX FIFO and Buffer Structure */
- /*struct FLEXCAN_RXFIFO_BUFFER_t RXFIFO;
- struct FLEXCAN_BUFFER_t BUF[56];*/
-/****************************************************************************/
-
- uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MI:32;
- } B;
- } RXIMR[64]; /* RX Individual Mask Registers */
-
- }; /* end of FLEXCAN_tag */
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name FlexCAN units references
- * @{
- */
-#if SPC5_HAS_FLEXCAN0 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_0 (*(volatile struct spc5_flexcan *)0xFFFC0000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN1 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_1 (*(volatile struct spc5_flexcan *)0xFFFC4000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN2 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_2 (*(volatile struct spc5_flexcan *)0xFFFC8000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN3 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_3 (*(volatile struct spc5_flexcan *)0xFFFCC000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN4 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_4 (*(volatile struct spc5_flexcan *)0xFFFD0000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN5 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_5 (*(volatile struct spc5_flexcan *)0xFFFD4000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_FLEXCAN_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c deleted file mode 100644 index 7a92b1044..000000000 --- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c +++ /dev/null @@ -1,1776 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file FlexPWM_v1/pwm_lld.c
- * @brief SPC5xx low level PWM driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the complex timer TIM1 when enabled.
- */
-#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer TIM2 when enabled.
- */
-#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer TIM3 when enabled.
- */
-#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief PWMD4 driver identifier.
- * @note The driver PWMD4 allocates the timer TIM4 when enabled.
- */
-#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief PWMD5 driver identifier.
- * @note The driver PWMD5 allocates the timer TIM5 when enabled.
- */
-#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/**
- * @brief PWMD6 driver identifier.
- * @note The driver PWMD6 allocates the timer TIM6 when enabled.
- */
-#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__)
-PWMDriver PWMD6;
-#endif
-
-/**
- * @brief PWMD7 driver identifier.
- * @note The driver PWMD7 allocates the timer TIM7 when enabled.
- */
-#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__)
-PWMDriver PWMD7;
-#endif
-
-/**
- * @brief PWMD8 driver identifier.
- * @note The driver PWMD8 allocates the timer TIM8 when enabled.
- */
-#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__)
-PWMDriver PWMD8;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active FlexPWM0 submodules.
- */
-static uint32_t flexpwm_active_submodules0;
-
-/**
- * @brief Number of active FlexPWM1 submodules.
- */
-static uint32_t flexpwm_active_submodules1;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Configures and activates the PWM peripheral submodule.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] sid PWM submodule identifier
- *
- * @notapi
- */
-void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
- pwmcnt_t pwmperiod;
- uint32_t psc;
-
- /* Clears Status Register.*/
- pwmp->flexpwmp->SUB[sid].STS.R = 0xFFFF;
-
- /* Clears LDOK and initializes the registers.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
- /* Setting PWM clock frequency and submodule prescaler.*/
- psc = SPC5_FLEXPWM0_CLK / pwmp->config->frequency;
-
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||
- (psc == 16) || (psc == 32) ||
- (psc == 64) || (psc == 128)),
- "pwm_lld_start_submodule(), #1", "invalid frequency");
-
- switch (psc) {
- case 1:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_1;
- break;
- case 2:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_2;
- break;
- case 4:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_4;
- break;
- case 8:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_8;
- break;
- case 16:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_16;
- break;
- case 32:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_32;
- break;
- case 64:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_64;
- break;
- case 128:
- pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_128;
- break;
- }
-
- /* Disables PWM FAULT function. */
- pwmp->flexpwmp->SUB[sid].DISMAP.R = 0;
- pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 1U;
-
- /* Sets PWM period.*/
- pwmperiod = pwmp->period;
- pwmp->flexpwmp->SUB[sid].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[sid].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[sid].VAL[1].R = pwmperiod / 2;
-
- /* Sets the submodule channels.*/
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting reloads.*/
- pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 0;
- pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 1;
-
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- case PWM_ALIGN_CENTER:
- /* Setting reloads.*/
- pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 1;
- pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 0;
- break;
- default:
- ;
- }
-
- /* Polarities setup.*/
- switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_LOW:
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
-
- /* Enables CHA mask and CHA.*/
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 0;
-
- /* Enables CHA mask and CHA.*/
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-
- break;
- case PWM_OUTPUT_DISABLED:
- /* Enables CHA mask.*/
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-
- break;
- default:
- ;
- }
- switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_LOW:
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
-
- /* Enables CHB mask and CHB.*/
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 0;
-
- /* Enables CHB mask and CHB.*/
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-
- break;
- case PWM_OUTPUT_DISABLED:
- /* Enables CHB mask.*/
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-
- break;
- default:
- ;
- }
-
- /* Complementary output setup.*/
- switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
- case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
- chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,
- "pwm_lld_start_submodule(), #2",
- "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
- pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
- break;
- case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
- chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,
- "pwm_lld_start_submodule(), #3",
- "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");
- pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
- break;
- default:
- ;
- }
-
- switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
- case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
- chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,
- "pwm_lld_start_submodule(), #4",
- "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");
- pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
- pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (1U << sid);
- pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
- break;
- case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
- chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,
- "pwm_lld_start_submodule(), #5",
- "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");
- pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
- pwmp->flexpwmp->MCTRL.B.IPOL |= 1U << sid;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
- break;
- default:
- ;
- }
-
- /* Sets the INIT and MASK registers.*/
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
- /* Updates SMOD registers and starts SMOD.*/
- pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid;
- pwmp->flexpwmp->MCTRL.B.RUN |= 1U << sid;
-}
-
-/**
- * @brief Enables a PWM channel of a submodule.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- * @param[in] sid PWM submodule id
- *
- * @notapi
- */
-void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width, uint8_t sid) {
- pwmcnt_t pwmperiod;
- int16_t nwidth;
- pwmperiod = pwmp->period;
- nwidth = width - (pwmperiod / 2);
-
- /* Clears LDOK.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
- /* Active the width interrupt.*/
- if (channel == 0) {
- if (pwmp->config->channels[0].callback != NULL) {
- if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 0) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x08;
- }
- }
-
- /* Sets the channel width.*/
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- if (nwidth >= 0)
- pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;
- else
- pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U;
- break;
- case PWM_ALIGN_CENTER:
- pwmp->flexpwmp->SUB[sid].VAL[3].R = width / 2;
- pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(width / 2) + 1U;
- break;
- default:
- ;
- }
-
- /* Removes the channel mask if it is necessary.*/
- if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) == 1)
- pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid);
-
- if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
- pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid);
- }
- }
- /* Active the width interrupt.*/
- else if (channel == 1) {
- if (pwmp->config->channels[1].callback != NULL) {
- if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 0) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x20;
- }
- }
- /* Sets the channel width.*/
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- if (nwidth >= 0)
- pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;
- else
- pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U;
- break;
- case PWM_ALIGN_CENTER:
- pwmp->flexpwmp->SUB[sid].VAL[5].R = width / 2;
- pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(width / 2) + 1U;
- break;
- default:
- ;
- }
-
- /* Removes the channel mask if it is necessary.*/
- if ((pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1)
- pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid);
-
- if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
- pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid);
- }
- }
-
- /* Active the periodic interrupt.*/
- if (pwmp->flexpwmp->SUB[sid].INTEN.B.RIE != 1U) {
- if (pwmp->config->callback != NULL) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 1;
- }
- }
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
- /* Forces reload of the VALUE registers.*/
- pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid;
-}
-
-/**
- * @brief Disables a PWM channel of a submodule.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] sid PWM submodule id
- *
- * @notapi
- */
-void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- uint8_t sid) {
-
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
- /* Disable the width interrupt.*/
- if (channel == 0) {
- if (pwmp->config->channels[0].callback != NULL) {
- if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 1) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x37;
- }
- }
-
- /* Active the channel mask.*/
- if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
- }
- else
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
- }
- /* Disable the width interrupt.*/
- else if (channel == 1) {
- if (pwmp->config->channels[1].callback != NULL) {
- if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 1) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x1F;
- }
- }
-
- /* Active the channel mask.*/
- if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
- pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
- }
- else
- pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
- }
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
- /* Disable RIE interrupt to prevent reload interrupt.*/
- if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) &&
- (pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1) {
- pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 0;
-
- /* Clear the reload flag.*/
- pwmp->flexpwmp->SUB[sid].STS.B.RF = 1U;
- }
-
- pwmp->flexpwmp->MCTRL.B.LDOK |= (1U << sid);
-}
-
-/**
- * @brief Common SMOD0...SMOD7 IRQ handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint16_t sr;
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[0].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[1].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[2].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R;
- if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08;
- pwmp->config->channels[0].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20;
- pwmp->config->channels[1].callback(pwmp);
- }
- if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
- pwmp->flexpwmp->SUB[3].STS.B.RF = 1U;
- pwmp->config->callback(pwmp);
- }
- }
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF0_HANDLER)
-#error "SPC5_FLEXPWM0_RF0_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD0 RF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF0_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD1);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF0_HANDLER)
-#error "SPC5_FLEXPWM0_COF0_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD0 COF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF0_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF1_HANDLER)
-#error "SPC5_FLEXPWM0_RF1_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD1 RF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD2);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF1_HANDLER)
-#error "SPC5_FLEXPWM0_COF1_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD1 COF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF2_HANDLER)
-#error "SPC5_FLEXPWM0_RF2_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD2 RF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD3);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF2_HANDLER)
-#error "SPC5_FLEXPWM0_COF2_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD2 COF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF3_HANDLER)
-#error "SPC5_FLEXPWM0_RF3_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD1 RF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD4);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF3_HANDLER)
-#error "SPC5_FLEXPWM0_COF3_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM0-SMOD1 COF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF0_HANDLER)
-#error "SPC5_FLEXPWM0_RF1_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD0 RF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF0_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD5);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF0_HANDLER)
-#error "SPC5_FLEXPWM1_COF0_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD0 COF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF0_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF1_HANDLER)
-#error "SPC5_FLEXPWM1_RF1_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD1 RF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD6);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF1_HANDLER)
-#error "SPC5_FLEXPWM1_COF1_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD1 COF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF2_HANDLER)
-#error "SPC5_FLEXPWM1_RF2_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD2 RF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD7);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF2_HANDLER)
-#error "SPC5_FLEXPWM1_COF2_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD2 COF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD7);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF3_HANDLER)
-#error "SPC5_FLEXPWM1_RF3_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD3 RF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD8);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF3_HANDLER)
-#error "SPC5_FLEXPWM1_COF3_HANDLER not defined"
-#endif
-/**
- * @brief FlexPWM1-SMOD3 COF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD8);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
- /* FlexPWM initially all not in use.*/
- flexpwm_active_submodules0 = 0;
- flexpwm_active_submodules1 = 0;
-
-#if (SPC5_PWM_USE_SMOD0)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD1);
- PWMD1.flexpwmp = &SPC5_FLEXPWM_0;
- INTC.PSR[SPC5_FLEXPWM0_RF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_COF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_CAF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD1)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD2);
- PWMD2.flexpwmp = &SPC5_FLEXPWM_0;
- INTC.PSR[SPC5_FLEXPWM0_RF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_COF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_CAF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD2)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD3);
- PWMD3.flexpwmp = &SPC5_FLEXPWM_0;
- INTC.PSR[SPC5_FLEXPWM0_RF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_COF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_CAF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD3)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD4);
- PWMD4.flexpwmp = &SPC5_FLEXPWM_0;
- INTC.PSR[SPC5_FLEXPWM0_RF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_COF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_CAF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD4)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD5);
- PWMD5.flexpwmp = &SPC5_FLEXPWM_1;
- INTC.PSR[SPC5_FLEXPWM1_RF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_COF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_CAF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD5)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD6);
- PWMD6.flexpwmp = &SPC5_FLEXPWM_1;
- INTC.PSR[SPC5_FLEXPWM1_RF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_COF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_CAF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD6)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD7);
- PWMD7.flexpwmp = &SPC5_FLEXPWM_1;
- INTC.PSR[SPC5_FLEXPWM1_RF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_COF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_CAF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD7)
- /* Driver initialization.*/
- pwmObjectInit(&PWMD8);
- PWMD8.flexpwmp = &SPC5_FLEXPWM_1;
- INTC.PSR[SPC5_FLEXPWM1_RF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_COF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_CAF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
- INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
- chDbgAssert(flexpwm_active_submodules0 < 5,
- "pwm_lld_start(), #1", "too many submodules");
- chDbgAssert(flexpwm_active_submodules1 < 5,
- "pwm_lld_start(), #2", "too many submodules");
-
- if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- flexpwm_active_submodules0++;
- }
-#endif /* SPC5_PWM_USE_SMOD0 */
-
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- flexpwm_active_submodules0++;
- }
-#endif /* SPC5_PWM_USE_SMOD1 */
-
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- flexpwm_active_submodules0++;
- }
-#endif /* SPC5_PWM_USE_SMOD2 */
-
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- flexpwm_active_submodules0++;
- }
-#endif /* SPC5_PWM_USE_SMOD3 */
-
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- flexpwm_active_submodules1++;
- }
-#endif /* SPC5_PWM_USE_SMOD4 */
-
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- flexpwm_active_submodules1++;
- }
-#endif /* SPC5_PWM_USE_SMOD5 */
-
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- flexpwm_active_submodules1++;
- }
-#endif /* SPC5_PWM_USE_SMOD6 */
-
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- flexpwm_active_submodules1++;
- }
-#endif /* SPC5_PWM_USE_SMOD7 */
-
- /**
- * If this is the first FlexPWM0 submodule
- * activated then the FlexPWM0 is enabled.
- */
-#if SPC5_PWM_USE_FLEXPWM0
- /* Set Peripheral Clock.*/
- if (flexpwm_active_submodules0 == 1) {
- halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
- SPC5_PWM_FLEXPWM0_START_PCTL);
- }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM1
- /* Set Peripheral Clock.*/
- if (flexpwm_active_submodules1 == 1) {
- halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL,
- SPC5_PWM_FLEXPWM1_START_PCTL);
- }
-#endif
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- pwm_lld_start_submodule(pwmp, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- pwm_lld_start_submodule(pwmp, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- pwm_lld_start_submodule(pwmp, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- pwm_lld_start_submodule(pwmp, 3);
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- pwm_lld_start_submodule(pwmp, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- pwm_lld_start_submodule(pwmp, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- pwm_lld_start_submodule(pwmp, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- pwm_lld_start_submodule(pwmp, 3);
- }
-#endif
- }
- else {
- /* Driver re-configuration scenario, it must be stopped first.*/
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xE;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xE;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xD;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xD;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xB;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xB;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0x7;
- pwmp->flexpwmp->MASK.B.MASKB &= 0x7;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xE;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xE;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xD;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xD;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0xB;
- pwmp->flexpwmp->MASK.B.MASKB &= 0xB;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- /* Disable the interrupts.*/
- pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-
- /* Disable the submodule.*/
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
- /* Active the submodule masks.*/
- pwmp->flexpwmp->MASK.B.MASKA &= 0x7;
- pwmp->flexpwmp->MASK.B.MASKB &= 0x7;
-
- /* Sets the MASK registers.*/
- pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U;
- pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U;
- }
-#endif
- }
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- chDbgAssert(flexpwm_active_submodules0 < 5,
- "pwm_lld_stop(), #1", "too many submodules");
- chDbgAssert(flexpwm_active_submodules1 < 5,
- "pwm_lld_stop(), #2", "too many submodules");
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- flexpwm_active_submodules0--;
- }
-#endif /* SPC5_PWM_USE_SMOD0 */
-
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- flexpwm_active_submodules0--;
- }
-#endif /* SPC5_PWM_USE_SMOD1 */
-
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- flexpwm_active_submodules0--;
- }
-#endif /* SPC5_PWM_USE_SMOD2 */
-
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- flexpwm_active_submodules0--;
- }
-#endif /* SPC5_PWM_USE_SMOD3 */
-
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- flexpwm_active_submodules1--;
- }
-#endif /* SPC5_PWM_USE_SMOD4 */
-
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- flexpwm_active_submodules1--;
- }
-#endif /* SPC5_PWM_USE_SMOD5 */
-
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- flexpwm_active_submodules1--;
- }
-#endif /* SPC5_PWM_USE_SMOD6 */
-
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- flexpwm_active_submodules1--;
- }
-#endif /* SPC5_PWM_USE_SMOD7 */
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
- pwmp->flexpwmp->SUB[0].INTEN.R = 0;
- pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xE;
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
- pwmp->flexpwmp->SUB[1].INTEN.R = 0;
- pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xD;
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
- pwmp->flexpwmp->SUB[2].INTEN.R = 0;
- pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xB;
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
- pwmp->flexpwmp->SUB[3].INTEN.R = 0;
- pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0x7;
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
- pwmp->flexpwmp->SUB[0].INTEN.R = 0;
- pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xE;
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
- pwmp->flexpwmp->SUB[1].INTEN.R = 0;
- pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xD;
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
- pwmp->flexpwmp->SUB[2].INTEN.R = 0;
- pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0xB;
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- /* SMOD stop.*/
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
- pwmp->flexpwmp->SUB[3].INTEN.R = 0;
- pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF;
- pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
- pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
- pwmp->flexpwmp->MCTRL.B.RUN &= 0x7;
- }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM0
- /* Disable peripheral clock if there is not an activated module.*/
- if (flexpwm_active_submodules0 == 0) {
- halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
- SPC5_PWM_FLEXPWM0_STOP_PCTL);
- }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM1
- /* Disable peripheral clock if there is not an activated module.*/
- if (flexpwm_active_submodules1 == 0) {
- halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL,
- SPC5_PWM_FLEXPWM1_STOP_PCTL);
- }
-#endif
-
- }
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 3);
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- pwm_lld_enable_submodule_channel(pwmp, channel, width, 3);
- }
-#endif
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 3);
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 0);
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 1);
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 2);
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- pwm_lld_disable_submodule_channel(pwmp, channel, 3);
- }
-#endif
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
- pwmcnt_t pwmperiod = period;
-#if SPC5_PWM_USE_SMOD0
- if (&PWMD1 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[0].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD1
- if (&PWMD2 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[1].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
-
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 2U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD2
- if (&PWMD3 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[2].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 4U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD3
- if (&PWMD4 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[3].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 8U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD4
- if (&PWMD5 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[0].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 1U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD5
- if (&PWMD6 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[1].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 2U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD6
- if (&PWMD7 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[2].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 4U;
- }
-#endif
-#if SPC5_PWM_USE_SMOD7
- if (&PWMD8 == pwmp) {
- pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-
- /* Setting PWM period.*/
- pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[3].VAL[0].R = 0;
- pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;
-
- switch (pwmp->config->mode & PWM_ALIGN_MASK) {
- case PWM_ALIGN_EDGE:
- /* Setting active front of PWM channels.*/
- pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;
- pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;
- break;
- default:
- ;
- }
- pwmp->flexpwmp->MCTRL.B.LDOK |= 8U;
- }
-#endif
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h deleted file mode 100644 index ea9acb7cd..000000000 --- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h +++ /dev/null @@ -1,475 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file FlexPWM_v1/pwm_lld.h
- * @brief SPC5xx low level PWM driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_flexpwm.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name STS register bits definitions
- * @{
- */
-#define SPC5_FLEXPWM_STS_CMPF0 (1U << 0)
-#define SPC5_FLEXPWM_STS_CMPF1 (1U << 1)
-#define SPC5_FLEXPWM_STS_CMPF2 (1U << 2)
-#define SPC5_FLEXPWM_STS_CMPF3 (1U << 3)
-#define SPC5_FLEXPWM_STS_CMPF4 (1U << 4)
-#define SPC5_FLEXPWM_STS_CMPF5 (1U << 5)
-#define SPC5_FLEXPWM_STS_CFX0 (1U << 6)
-#define SPC5_FLEXPWM_STS_CFX1 (1U << 7)
-#define SPC5_FLEXPWM_STS_RF (1U << 12)
-#define SPC5_FLEXPWM_STS_REF (1U << 13)
-#define SPC5_FLEXPWM_STS_RUF (1U << 14)
-/** @} */
-
-/**
- * @name PSC values definition
- * @{
- */
-#define SPC5_FLEXPWM_PSC_1 0U
-#define SPC5_FLEXPWM_PSC_2 1U
-#define SPC5_FLEXPWM_PSC_4 2U
-#define SPC5_FLEXPWM_PSC_8 3U
-#define SPC5_FLEXPWM_PSC_16 4U
-#define SPC5_FLEXPWM_PSC_32 5U
-#define SPC5_FLEXPWM_PSC_64 6U
-#define SPC5_FLEXPWM_PSC_128 7U
-/** @} */
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 2
-
-/**
- * @brief Complementary output modes mask.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0
-
-/**
- * @brief Complementary output not driven.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00
-
-/**
- * @brief Complementary output, active is logic level one.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10
-
-/**
- * @brief Complementary output, active is logic level zero.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20
-
-/**
- * @brief Alignment mode mask.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_MASK 0x01
-
-/**
- * @brief Edge-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE 0x00
-
-/**
- * @brief Center-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER 0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD0 FALSE
-#endif
-
-/**
- * @brief PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD1 FALSE
-#endif
-
-/**
- * @brief PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD2) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD2 FALSE
-#endif
-
-/**
- * @brief PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD3) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD3 FALSE
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD0_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD1_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD2_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD3_PRIORITY 7
-#endif
-
-/**
- * @brief FlexPWM-0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief FlexPWM-0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD4) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD4 FALSE
-#endif
-
-/**
- * @brief PWMD6 driver enable switch.
- * @details If set to @p TRUE the support for PWMD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD5) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD5 FALSE
-#endif
-
-/**
- * @brief PWMD7 driver enable switch.
- * @details If set to @p TRUE the support for PWMD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD6) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD6 FALSE
-#endif
-
-/**
- * @brief PWMD8 driver enable switch.
- * @details If set to @p TRUE the support for PWMD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD7) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD7 FALSE
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD4_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD4_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD6 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD5_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD7 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD6_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD6_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD8 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD7_PRIORITY 7
-#endif
-
-/**
- * @brief FlexPWM-1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief FlexPWM-1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#define SPC5_PWM_USE_FLEXPWM0 (SPC5_PWM_USE_SMOD0 || \
- SPC5_PWM_USE_SMOD1 || \
- SPC5_PWM_USE_SMOD2 || \
- SPC5_PWM_USE_SMOD3)
-
-#define SPC5_PWM_USE_FLEXPWM1 (SPC5_PWM_USE_SMOD4 || \
- SPC5_PWM_USE_SMOD5 || \
- SPC5_PWM_USE_SMOD6 || \
- SPC5_PWM_USE_SMOD7)
-
-#if !SPC5_HAS_FLEXPWM0 && SPC5_PWM_USE_FLEXPWM0
-#error "FlexPWM0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_FLEXPWM1 && SPC5_PWM_USE_FLEXPWM1
-#error "FlexPWM1 not present in the selected device"
-#endif
-
-#if !SPC5_PWM_USE_FLEXPWM0 && !SPC5_PWM_USE_FLEXPWM1
-#error "PWM driver activated but no PWM peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
- /**
- * @brief PWM functional mode.
- */
- pwmmode_t mode;
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @Pointer to the volatile FlexPWM registers block.
- */
- volatile struct spc5_flexpwm *flexpwmp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_SMOD0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_SMOD1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_SMOD2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_SMOD3 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_SMOD4 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#if SPC5_PWM_USE_SMOD5 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD6;
-#endif
-
-#if SPC5_PWM_USE_SMOD6 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD7;
-#endif
-
-#if SPC5_PWM_USE_SMOD7 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD8;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h deleted file mode 100644 index 5be53d949..000000000 --- a/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h +++ /dev/null @@ -1,491 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file FlexPWM_v1/spc5_flexpwm.h
- * @brief SPC5xx FlexPWM header file.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _SPC5_FLEXPWM_H_
-#define _SPC5_FLEXPWM_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief SPC5 FlexPWM registers block.
- * @note Redefined from the SPC5 headers because the non uniform
- * declaration of the SubModules registers among the various
- * sub-families.
- */
-struct spc5_flexpwm_submodule {
-
- union {
- vuint16_t R;
- } CNT; /* Counter Register */
-
- union {
- vuint16_t R;
- } INIT; /* Initial Count Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t DBGEN :1;
- vuint16_t WAITEN :1;
- vuint16_t INDEP :1;
- vuint16_t PWMA_INIT :1;
- vuint16_t PWMB_INIT :1;
- vuint16_t PWMX_INIT :1;
- vuint16_t INIT_SEL :2;
- vuint16_t FRCEN :1;
- vuint16_t FORCE :1;
- vuint16_t FORCE_SEL :3;
- vuint16_t RELOAD_SEL :1;
- vuint16_t CLK_SEL :2;
- } B;
- } CTRL2; /* Control 2 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t LDFQ :4;
- vuint16_t HALF :1;
- vuint16_t FULL :1;
- vuint16_t DT :2;
- vuint16_t :1;
- vuint16_t PRSC :3;
- vuint16_t :3;
- vuint16_t DBLEN :1;
- } B;
- } CTRL; /* Control Register */
-
- union {
- vuint16_t R;
- } VAL[6]; /* Value Register 0->5 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t FRACAEN :1;
- vuint16_t :10;
- vuint16_t FRACADLY :5;
- } B;
- } FRACA; /* Fractional Delay Register A */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t FRACBEN :1;
- vuint16_t :10;
- vuint16_t FRACBDLY :5;
- } B;
- } FRACB; /* Fractional Delay Register B */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t PWMA_IN :1;
- vuint16_t PWMB_IN :1;
- vuint16_t PWMX_IN :1;
- vuint16_t :2;
- vuint16_t POLA :1;
- vuint16_t POLB :1;
- vuint16_t POLX :1;
- vuint16_t :2;
- vuint16_t PWMAFS :2;
- vuint16_t PWMBFS :2;
- vuint16_t PWMXFS :2;
- } B;
- } OCTRL; /* Output Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :1;
- vuint16_t RUF :1;
- vuint16_t REF :1;
- vuint16_t RF :1;
- vuint16_t CFA1 :1;
- vuint16_t CFA0 :1;
- vuint16_t CFB1 :1;
- vuint16_t CFB0 :1;
- vuint16_t CFX1 :1;
- vuint16_t CFX0 :1;
- vuint16_t CMPF :6;
- } B;
- } STS; /* Status Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :2;
- vuint16_t REIE :1;
- vuint16_t RIE :1;
- vuint16_t :4;
- vuint16_t CX1IE :1;
- vuint16_t CX0IE :1;
- vuint16_t CMPIE :6;
- } B;
- } INTEN; /* Interrupt Enable Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :6;
- vuint16_t VALDE :1;
- vuint16_t FAND :1;
- vuint16_t CAPTDE :2;
- vuint16_t CA1DE :1;
- vuint16_t CA0DE :1;
- vuint16_t CB1DE :1;
- vuint16_t CB0DE :1;
- vuint16_t CX1DE :1;
- vuint16_t CX0DE :1;
- } B;
- } DMAEN; /* DMA Enable Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :10;
- vuint16_t OUT_TRIG_EN :6;
- } B;
- } TCTRL; /* Output Trigger Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :4;
- vuint16_t DISX :4;
- vuint16_t DISB :4;
- vuint16_t DISA :4;
- } B;
- } DISMAP; /* Fault Disable Mapping Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t DTCNT0 :11;
- } B;
- } DTCNT0; /* Deadtime Count Register 0 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t DTCNT1 :11;
- } B;
- } DTCNT1; /* Deadtime Count Register 1 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CA1CNT :3;
- vuint16_t CA0CNT :3;
- vuint16_t CFAWM :2;
- vuint16_t EDGCNTAEN :1;
- vuint16_t INPSELA :1;
- vuint16_t EDGA1 :2;
- vuint16_t EDGA0 :2;
- vuint16_t ONESHOTA :1;
- vuint16_t ARMA :1;
- } B;
- } CAPTCTRLA; /* Capture Control Register A */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t EDGCNTA :8;
- vuint16_t EDGCMPA :8;
- } B;
- } CAPTCOMPA; /* Capture Compare Register A */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CB1CNT :3;
- vuint16_t CB0CNT :3;
- vuint16_t CFBWM :2;
- vuint16_t EDGCNTBEN :1;
- vuint16_t INPSELB :1;
- vuint16_t EDGB1 :2;
- vuint16_t EDGB0 :2;
- vuint16_t ONESHOTB :1;
- vuint16_t ARMB :1;
- } B;
- } CAPTCTRLB; /* Capture Control Register B */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t EDGCNTB :8;
- vuint16_t EDGCMPB :8;
- } B;
- } CAPTCOMPB; /* Capture Compare Register B */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CX1CNT :3;
- vuint16_t CX0CNT :3;
- vuint16_t CFXWM :2;
- vuint16_t EDGCNTX_EN :1;
- vuint16_t INP_SELX :1;
- vuint16_t EDGX1 :2;
- vuint16_t EDGX0 :2;
- vuint16_t ONESHOTX :1;
- vuint16_t ARMX :1;
- } B;
- } CAPTCTRLX; /* Capture Control Register B */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t EDGCNTX :8;
- vuint16_t EDGCMPX :8;
- } B;
- } CAPTCOMPX; /* Capture Compare Register X */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL0 :16;
- } B;
- } CVAL0; /* Capture Value 0 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL0CYC :4;
- } B;
- } CVAL0C; /* Capture Value 0 Cycle Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL1 :16;
- } B;
- } CVAL1; /* Capture Value 1 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL1CYC :4;
- } B;
- } CVAL1C; /* Capture Value 1 Cycle Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL2 :16;
- } B;
- } CVAL2; /* Capture Value 2 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL2CYC :4;
- } B;
- } CVAL2C; /* Capture Value 2 Cycle Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL3 :16;
- } B;
- } CVAL3; /* Capture Value 3 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL3CYC :4;
- } B;
- } CVAL3C; /* Capture Value 3 Cycle Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL4 :16;
- } B;
- } CVAL4; /* Capture Value 4 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL4CYC :4;
- } B;
- } CVAL4C; /* Capture Value 4 Cycle Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPTVAL5 :16;
- } B;
- } CVAL5; /* Capture Value 5 Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t CVAL5CYC :4;
- } B;
- } CVAL5C; /* Capture Value 5 Cycle Register */
-
- uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
-
-};
-/* end of FLEXPWM_SUB_tag */
-
-struct spc5_flexpwm {
-
- struct spc5_flexpwm_submodule SUB[4];
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :4;
- vuint16_t PWMA_EN :4;
- vuint16_t PWMB_EN :4;
- vuint16_t PWMX_EN :4;
- } B;
- } OUTEN; /* Output Enable Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :4;
- vuint16_t MASKA :4;
- vuint16_t MASKB :4;
- vuint16_t MASKX :4;
- } B;
- } MASK; /* Output Mask Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :8;
- vuint16_t OUTA_3 :1;
- vuint16_t OUTB_3 :1;
- vuint16_t OUTA_2 :1;
- vuint16_t OUTB_2 :1;
- vuint16_t OUTA_1 :1;
- vuint16_t OUTB_1 :1;
- vuint16_t OUTA_0 :1;
- vuint16_t OUTB_0 :1;
- } B;
- } SWCOUT; /* Software Controlled Output Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t SELA_3 :2;
- vuint16_t SELB_3 :2;
- vuint16_t SELA_2 :2;
- vuint16_t SELB_2 :2;
- vuint16_t SELA_1 :2;
- vuint16_t SELB_1 :2;
- vuint16_t SELA_0 :2;
- vuint16_t SELB_0 :2;
- } B;
- } DTSRCSEL; /* Deadtime Source Select Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t IPOL :4;
- vuint16_t RUN :4;
- vuint16_t CLDOK :4;
- vuint16_t LDOK :4;
- } B;
- } MCTRL; /* Master Control Register */
-
- int16_t FLEXPWM_reserved1;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t FLVL :4;
- vuint16_t FAUTO :4;
- vuint16_t FSAFE :4;
- vuint16_t FIE :4;
- } B;
- } FCTRL; /* Fault Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t FTEST :1;
- vuint16_t FFPIN :4;
- vuint16_t :4;
- vuint16_t FFLAG :4;
- } B;
- } FSTS; /* Fault Status Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t FILT_CNT :3;
- vuint16_t FILT_PER :8;
- } B;
- } FFILT; /* Fault FilterRegister */
-
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name FlexPWM units references
- * @{
- */
-#if SPC5_HAS_FLEXPWM0 || defined(__DOXYGEN__)
-#define SPC5_FLEXPWM_0 (*(volatile struct spc5_flexpwm *)0xFFE24000UL)
-#endif
-
-#if SPC5_HAS_FLEXPWM1 || defined(__DOXYGEN__)
-#define SPC5_FLEXPWM_1 (*(volatile struct spc5_flexpwm *)0xFFE28000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_FLEXPWM_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c deleted file mode 100644 index 71247b236..000000000 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c +++ /dev/null @@ -1,602 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/LINFlex_v1/serial_lld.c
- * @brief SPC5xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief LIINFlex-0 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief LIINFlex-1 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/**
- * @brief LIINFlex-2 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/**
- * @brief LIINFlex-3 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-SerialDriver SD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- SERIAL_DEFAULT_BITRATE,
- SD_MODE_8BITS_PARITY_NONE
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief LINFlex initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration
- */
-static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
- uint32_t div;
- volatile struct spc5_linflex *linflexp = sdp->linflexp;
-
- /* Enters the configuration mode.*/
- linflexp->LINCR1.R = 1; /* INIT bit. */
-
- /* Configures the LINFlex in UART mode with all the required
- parameters.*/
- linflexp->UARTCR.R = SPC5_UARTCR_UART; /* UART mode FIRST. */
- linflexp->UARTCR.R = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode;
- div = SPC5_LINFLEX0_CLK / config->speed;
- linflexp->LINFBRR.R = (uint16_t)(div & 15); /* Fractional divider. */
- linflexp->LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */
- linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/
- linflexp->LINIER.R = SPC5_LINIER_DTIE | SPC5_LINIER_DRIE |
- SPC5_LINIER_BOIE | SPC5_LINIER_FEIE |
- SPC5_LINIER_SZIE; /* Interrupts enabled. */
-
- /* Leaves the configuration mode.*/
- linflexp->LINCR1.R = 0;
-}
-
-/**
- * @brief LINFlex de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] linflexp pointer to a LINFlex I/O block
- */
-static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) {
-
- /* Enters the configuration mode.*/
- linflexp->LINCR1.R = 1; /* INIT bit. */
-
- /* Resets the LINFlex registers.*/
- linflexp->LINFBRR.R = 0; /* Fractional divider. */
- linflexp->LINIBRR.R = 0; /* Integer divider. */
- linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/
- linflexp->UARTCR.R = SPC5_UARTCR_UART;
- linflexp->LINIER.R = 0; /* Interrupts disabled. */
-
- /* Leaves the configuration mode.*/
- linflexp->LINCR1.R = 0;
-}
-
-/**
- * @brief Common RXI IRQ handler.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_rxi_interrupt(SerialDriver *sdp) {
- flagsmask_t sts = 0;
- uint16_t sr = sdp->linflexp->UARTSR.R;
-
- sdp->linflexp->UARTSR.R = SPC5_UARTSR_NF | SPC5_UARTSR_DRF |
- SPC5_UARTSR_PE0;
- if (sr & SPC5_UARTSR_NF)
- sts |= SD_NOISE_ERROR;
- if (sr & SPC5_UARTSR_PE0)
- sts |= SD_PARITY_ERROR;
- chSysLockFromIsr();
- if (sts)
- chnAddFlagsI(sdp, sts);
- if (sr & SPC5_UARTSR_DRF) {
- sdIncomingDataI(sdp, sdp->linflexp->BDRM.B.DATA4);
- sdp->linflexp->UARTSR.R = SPC5_UARTSR_RMB;
- }
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Common TXI IRQ handler.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_txi_interrupt(SerialDriver *sdp) {
- msg_t b;
-
- sdp->linflexp->UARTSR.R = SPC5_UARTSR_DTF;
- chSysLockFromIsr();
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- sdp->linflexp->UARTCR.B.TXEN = 0;
- }
- else
- sdp->linflexp->BDRL.B.DATA0 = b;
- chSysUnlockFromIsr();
-}
-
-/**
- * @brief Common ERR IRQ handler.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_err_interrupt(SerialDriver *sdp) {
- flagsmask_t sts = 0;
- uint16_t sr = sdp->linflexp->UARTSR.R;
-
- sdp->linflexp->UARTSR.R = SPC5_UARTSR_BOF | SPC5_UARTSR_FEF |
- SPC5_UARTSR_SZF;
- if (sr & SPC5_UARTSR_BOF)
- sts |= SD_OVERRUN_ERROR;
- if (sr & SPC5_UARTSR_FEF)
- sts |= SD_FRAMING_ERROR;
- if (sr & SPC5_UARTSR_SZF)
- sts |= SD_BREAK_DETECTED;
- chSysLockFromIsr();
- chnAddFlagsI(sdp, sts);
- chSysUnlockFromIsr();
-}
-
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
- (void)qp;
- if (!SD1.linflexp->UARTCR.B.TXEN) {
- msg_t b = sdRequestDataI(&SD1);
- if (b != Q_EMPTY) {
- SD1.linflexp->UARTCR.B.TXEN = 1;
- SD1.linflexp->BDRL.B.DATA0 = b;
- }
- }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
- (void)qp;
- if (!SD2.linflexp->UARTCR.B.TXEN) {
- msg_t b = sdRequestDataI(&SD2);
- if (b != Q_EMPTY) {
- SD2.linflexp->UARTCR.B.TXEN = 1;
- SD2.linflexp->BDRL.B.DATA0 = b;
- }
- }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
- (void)qp;
- if (!SD3.linflexp->UARTCR.B.TXEN) {
- msg_t b = sdRequestDataI(&SD3);
- if (b != Q_EMPTY) {
- SD3.linflexp->UARTCR.B.TXEN = 1;
- SD3.linflexp->BDRL.B.DATA0 = b;
- }
- }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
- (void)qp;
- if (!SD4.linflexp->UARTCR.B.TXEN) {
- msg_t b = sdRequestDataI(&SD4);
- if (b != Q_EMPTY) {
- SD4.linflexp->UARTCR.B.TXEN = 1;
- SD4.linflexp->BDRL.B.DATA0 = b;
- }
- }
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX0_RXI_HANDLER)
-#error "SPC5_LINFLEX0_RXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-0 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_RXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_rxi_interrupt(&SD1);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX0_TXI_HANDLER)
-#error "SPC5_LINFLEX0_TXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-0 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_TXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_txi_interrupt(&SD1);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX0_ERR_HANDLER)
-#error "SPC5_LINFLEX0_ERR_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-0 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_ERR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_err_interrupt(&SD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX1_RXI_HANDLER)
-#error "SPC5_LINFLEX1_RXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-1 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_RXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_rxi_interrupt(&SD2);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX1_TXI_HANDLER)
-#error "SPC5_LINFLEX1_TXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-1 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_TXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_txi_interrupt(&SD2);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX1_ERR_HANDLER)
-#error "SPC5_LINFLEX1_ERR_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-1 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_err_interrupt(&SD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX2_RXI_HANDLER)
-#error "SPC5_LINFLEX2_RXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-2 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_rxi_interrupt(&SD3);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX2_TXI_HANDLER)
-#error "SPC5_LINFLEX2_TXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-2 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_txi_interrupt(&SD3);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX2_ERR_HANDLER)
-#error "SPC5_LINFLEX2_ERR_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-2 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_err_interrupt(&SD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX3_RXI_HANDLER)
-#error "SPC5_LINFLEX3_RXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-3 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_rxi_interrupt(&SD4);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX3_TXI_HANDLER)
-#error "SPC5_LINFLEX3_TXI_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-3 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_txi_interrupt(&SD4);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX3_ERR_HANDLER)
-#error "SPC5_LINFLEX3_ERR_HANDLER not defined"
-#endif
-/**
- * @brief LINFlex-3 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- spc5xx_serve_err_interrupt(&SD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if SPC5_SERIAL_USE_LINFLEX0
- sdObjectInit(&SD1, NULL, notify1);
- SD1.linflexp = &SPC5_LINFLEX0;
- INTC.PSR[SPC5_LINFLEX0_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
- INTC.PSR[SPC5_LINFLEX0_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
- INTC.PSR[SPC5_LINFLEX0_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1
- sdObjectInit(&SD2, NULL, notify2);
- SD2.linflexp = &SPC5_LINFLEX1;
- INTC.PSR[SPC5_LINFLEX1_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
- INTC.PSR[SPC5_LINFLEX1_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
- INTC.PSR[SPC5_LINFLEX1_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2
- sdObjectInit(&SD3, NULL, notify3);
- SD3.linflexp = &SPC5_LINFLEX2;
- INTC.PSR[SPC5_LINFLEX2_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
- INTC.PSR[SPC5_LINFLEX2_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
- INTC.PSR[SPC5_LINFLEX2_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3
- sdObjectInit(&SD4, NULL, notify4);
- SD4.linflexp = &SPC5_LINFLEX3;
- INTC.PSR[SPC5_LINFLEX3_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
- INTC.PSR[SPC5_LINFLEX3_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
- INTC.PSR[SPC5_LINFLEX3_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
-#if SPC5_SERIAL_USE_LINFLEX0
- if (&SD1 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
- SPC5_SERIAL_LINFLEX0_START_PCTL);
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1
- if (&SD2 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
- SPC5_SERIAL_LINFLEX1_START_PCTL);
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2
- if (&SD3 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
- SPC5_SERIAL_LINFLEX2_START_PCTL);
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3
- if (&SD4 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
- SPC5_SERIAL_LINFLEX3_START_PCTL);
- }
-#endif
- }
- spc5_linflex_init(sdp, config);
-}
-
-/**
- * @brief Low level serial driver stop.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- spc5_linflex_deinit(sdp->linflexp);
-
-#if SPC5_SERIAL_USE_LINFLEX0
- if (&SD1 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
- SPC5_SERIAL_LINFLEX0_STOP_PCTL);
- return;
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1
- if (&SD2 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
- SPC5_SERIAL_LINFLEX1_STOP_PCTL);
- return;
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2
- if (&SD3 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
- SPC5_SERIAL_LINFLEX2_STOP_PCTL);
- return;
- }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3
- if (&SD4 == sdp) {
- halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
- SPC5_SERIAL_LINFLEX3_STOP_PCTL);
- return;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h deleted file mode 100644 index cbd446b86..000000000 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h +++ /dev/null @@ -1,302 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/LINFlex_v1/serial_lld.h
- * @brief SPC5xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "spc5_linflex.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Serial driver allowable modes
- * @{
- */
-#define SD_MODE_8BITS_PARITY_NONE (SPC5_UARTCR_WL)
-#define SD_MODE_8BITS_PARITY_EVEN (SPC5_UARTCR_WL | \
- SPC5_UARTCR_PCE)
-#define SD_MODE_8BITS_PARITY_ODD (SPC5_UARTCR_WL | \
- SPC5_UARTCR_PCE | \
- SPC5_UARTCR_OP)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief LINFlex-0 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-0 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX0 FALSE
-#endif
-
-/**
- * @brief LINFlex-1 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-1 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX1 FALSE
-#endif
-
-/**
- * @brief LINFlex-2 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-2 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX2 FALSE
-#endif
-
-/**
- * @brief LINFlex-3 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-3 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX3 FALSE
-#endif
-
-/**
- * @brief LINFlex-0 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
-#endif
-
-/**
- * @brief LINFlex-1 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
-#endif
-
-/**
- * @brief LINFlex-2 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_PRIORITY 8
-#endif
-
-/**
- * @brief LINFlex-3 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_PRIORITY 8
-#endif
-
-/**
- * @brief LINFlex-0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief LINFlex-0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief LINFlex-1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief LINFlex-1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief LINFlex-2 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief LINFlex-2 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief LINFlex-3 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief LINFlex-3 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 && !SPC5_HAS_LINFLEX0
-#error "LINFlex-0 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 && !SPC5_HAS_LINFLEX1
-#error "LINFlex-1 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 && !SPC5_HAS_LINFLEX2
-#error "LINFlex-2 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 && !SPC5_HAS_LINFLEX3
-#error "LINFlex-3 not present in the selected device"
-#endif
-
-#if !SPC5_SERIAL_USE_LINFLEX0 && !SPC5_SERIAL_USE_LINFLEX1 && \
- !SPC5_SERIAL_USE_LINFLEX2 && !SPC5_SERIAL_USE_LINFLEX3
-#error "SERIAL driver activated but no LINFlex peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note This structure content is architecture dependent, each driver
- * implementation defines its own version and the custom static
- * initializers.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t speed;
- /**
- * @brief Mode flags.
- */
- uint8_t mode;
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- InputQueue iqueue; \
- /* Output queue.*/ \
- OutputQueue oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the volatile LINFlex registers block.*/ \
- volatile struct spc5_linflex *linflexp;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h deleted file mode 100644 index 28e7575c4..000000000 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h +++ /dev/null @@ -1,510 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/spc5_linflex.h
- * @brief LINFlex helper driver header.
- *
- * @addtogroup SPC5xx_LINFLEX
- * @{
- */
-
-#ifndef _SPC5_LINFLEX_H_
-#define _SPC5_LINFLEX_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name LINIER register bits definitions
- * @{
- */
-#define SPC5_LINIER_HRIE (1U << 0)
-#define SPC5_LINIER_DTIE (1U << 1)
-#define SPC5_LINIER_DRIE (1U << 2)
-#define SPC5_LINIER_DBEIE (1U << 3)
-#define SPC5_LINIER_DBFIE (1U << 4)
-#define SPC5_LINIER_WUIE (1U << 5)
-#define SPC5_LINIER_LSIE (1U << 6)
-#define SPC5_LINIER_BOIE (1U << 7)
-#define SPC5_LINIER_FEIE (1U << 8)
-#define SPC5_LINIER_HEIE (1U << 11)
-#define SPC5_LINIER_CEIE (1U << 12)
-#define SPC5_LINIER_BEIE (1U << 13)
-#define SPC5_LINIER_OCIE (1U << 14)
-#define SPC5_LINIER_SZIE (1U << 15)
-/** @} */
-
-/**
- * @name UARTSR register bits definitions
- * @{
- */
-#define SPC5_UARTSR_NF (1U << 0)
-#define SPC5_UARTSR_DTF (1U << 1)
-#define SPC5_UARTSR_DRF (1U << 2)
-#define SPC5_UARTSR_WUF (1U << 5)
-#define SPC5_UARTSR_RPS (1U << 6)
-#define SPC5_UARTSR_BOF (1U << 7)
-#define SPC5_UARTSR_FEF (1U << 8)
-#define SPC5_UARTSR_RMB (1U << 9)
-#define SPC5_UARTSR_PE0 (1U << 10)
-#define SPC5_UARTSR_PE1 (1U << 11)
-#define SPC5_UARTSR_PE2 (1U << 12)
-#define SPC5_UARTSR_PE3 (1U << 13)
-#define SPC5_UARTSR_OCF (1U << 14)
-#define SPC5_UARTSR_SZF (1U << 15)
-/** @} */
-
-/**
- * @name UARTCR register bits definitions
- * @{
- */
-#define SPC5_UARTCR_UART (1U << 0)
-#define SPC5_UARTCR_WL (1U << 1)
-#define SPC5_UARTCR_PCE (1U << 2)
-#define SPC5_UARTCR_OP (1U << 3)
-#define SPC5_UARTCR_TXEN (1U << 4)
-#define SPC5_UARTCR_RXEN (1U << 5)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-
-struct spc5_linflex {
-
- int16_t LINFLEX_reserved1;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CCD :1;
- vuint16_t CFD :1;
- vuint16_t LASE :1;
- vuint16_t AWUM :1;
- vuint16_t MBL :4;
- vuint16_t BF :1;
- vuint16_t SFTM :1;
- vuint16_t LBKM :1;
- vuint16_t MME :1;
- vuint16_t SBDT :1;
- vuint16_t RBLM :1;
- vuint16_t SLEEP :1;
- vuint16_t INIT :1;
- } B;
- } LINCR1;
-
- int16_t LINFLEX_reserved2;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t SZIE :1;
- vuint16_t OCIE :1;
- vuint16_t BEIE :1;
- vuint16_t CEIE :1;
- vuint16_t HEIE :1;
- vuint16_t :2;
- vuint16_t FEIE :1;
- vuint16_t BOIE :1;
- vuint16_t LSIE :1;
- vuint16_t WUIE :1;
- vuint16_t DBFIE :1;
- vuint16_t DBEIE :1;
- vuint16_t DRIE :1;
- vuint16_t DTIE :1;
- vuint16_t HRIE :1;
- } B;
- } LINIER;
-
- int16_t LINFLEX_reserved3;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t LINS :4;
- vuint16_t :2;
- vuint16_t RMB :1;
- vuint16_t :1;
- vuint16_t RBSY :1;
- vuint16_t RPS :1;
- vuint16_t WUF :1;
- vuint16_t DBFF :1;
- vuint16_t DBEF :1;
- vuint16_t DRF :1;
- vuint16_t DTF :1;
- vuint16_t HRF :1;
- } B;
- } LINSR;
-
- int16_t LINFLEX_reserved4;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t SZF :1;
- vuint16_t OCF :1;
- vuint16_t BEF :1;
- vuint16_t CEF :1;
- vuint16_t SFEF :1;
- vuint16_t BDEF :1;
- vuint16_t IDPEF :1;
- vuint16_t FEF :1;
- vuint16_t BOF :1;
- vuint16_t :6;
- vuint16_t NF :1;
- } B;
- } LINESR;
-
- int16_t LINFLEX_reserved5;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :1;
- vuint16_t TDFL :2;
- vuint16_t :1;
- vuint16_t RDFL :2;
- vuint16_t :4;
- vuint16_t RXEN :1;
- vuint16_t TXEN :1;
- vuint16_t OP :1;
- vuint16_t PCE :1;
- vuint16_t WL :1;
- vuint16_t UART :1;
- } B;
- } UARTCR;
-
- int16_t LINFLEX_reserved6;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t SZF :1;
- vuint16_t OCF :1;
- vuint16_t PE :4;
- vuint16_t RMB :1;
- vuint16_t FEF :1;
- vuint16_t BOF :1;
- vuint16_t RPS :1;
- vuint16_t WUF :1;
- vuint16_t :2;
- vuint16_t DRF :1;
- vuint16_t DTF :1;
- vuint16_t NF :1;
- } B;
- } UARTSR;
-
- int16_t LINFLEX_reserved7;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t LTOM :1;
- vuint16_t IOT :1;
- vuint16_t TOCE :1;
- vuint16_t CNT :8;
- } B;
- } LINTCSR;
-
- int16_t LINFLEX_reserved8;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t OC2 :8;
- vuint16_t OC1 :8;
- } B;
- } LINOCR;
-
- int16_t LINFLEX_reserved9;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :4;
- vuint16_t RTO :4;
- vuint16_t :1;
- vuint16_t HTO :7;
- } B;
- } LINTOCR;
-
- int16_t LINFLEX_reserved10;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t DIV_F :4;
- } B;
- } LINFBRR;
-
- int16_t LINFLEX_reserved11;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DIV_M :13;
- } B;
- } LINIBRR;
-
- int16_t LINFLEX_reserved12;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :8;
- vuint16_t CF :8;
- } B;
- } LINCFR;
-
- int16_t LINFLEX_reserved13;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :1;
- vuint16_t IOBE :1;
- vuint16_t IOPE :1;
- vuint16_t WURQ :1;
- vuint16_t DDRQ :1;
- vuint16_t DTRQ :1;
- vuint16_t ABRQ :1;
- vuint16_t HTRQ :1;
- vuint16_t :8;
- } B;
- } LINCR2;
-
- int16_t LINFLEX_reserved14;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t DFL :6;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } BIDR;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t DATA3 :8;
- vuint32_t DATA2 :8;
- vuint32_t DATA1 :8;
- vuint32_t DATA0 :8;
- } B;
- } BDRL;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t DATA7 :8;
- vuint32_t DATA6 :8;
- vuint32_t DATA5 :8;
- vuint32_t DATA4 :8;
- } B;
- } BDRM;
-
- int16_t LINFLEX_reserved15;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :8;
- vuint16_t FACT :8;
- } B;
- } IFER;
-
- int16_t LINFLEX_reserved16;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t IFMI :4;
- } B;
- } IFMI;
-
- int16_t LINFLEX_reserved17;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :12;
- vuint16_t IFM :4;
- } B;
- } IFMR;
-
- int16_t LINFLEX_reserved18;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR0;
-
- int16_t LINFLEX_reserved19;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR1;
-
- int16_t LINFLEX_reserved20;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR2;
-
- int16_t LINFLEX_reserved21;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR3;
-
- int16_t LINFLEX_reserved22;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR4;
-
- int16_t LINFLEX_reserved23;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR5;
-
- int16_t LINFLEX_reserved24;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR6;
-
- int16_t LINFLEX_reserved25;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t DFL :3;
- vuint16_t DIR :1;
- vuint16_t CCS :1;
- vuint16_t :2;
- vuint16_t ID :6;
- } B;
- } IFCR7;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-/**
- * @name LINFlex units references
- * @{
- */
-#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE40000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE44000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFFE48000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFFE4C000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_LINFLEX_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c deleted file mode 100644 index d8ae4b2d5..000000000 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c +++ /dev/null @@ -1,173 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/SIUL_v1/pal_lld.c
- * @brief SPC5xx SIUL low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if defined(SPC5_SIUL_SYSTEM_PINS)
-static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief SPC5xx I/O ports configuration.
- *
- * @param[in] config the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
- unsigned i;
-
-#if defined(SPC5_SIUL_PCTL)
- /* SIUL clock gating if present.*/
- halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL,
- SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
-#endif
-
- /* Initialize PCR registers for undefined pads.*/
- for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) {
-#if defined(SPC5_SIUL_SYSTEM_PINS)
- /* Handling the case where some SIU pins are not meant to be reprogrammed,
- for example JTAG pins.*/
- unsigned j;
- for (j = 0; j < sizeof system_pins; j++) {
- if (i == system_pins[j])
- goto skip;
- }
- SIU.PCR[i].R = config->default_mode;
-skip:
- ;
-#else
- SIU.PCR[i].R = config->default_mode;
-#endif
- }
-
- /* Initialize PADSEL registers.*/
- for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++)
- SIU.PSMI[i].R = config->padsels[i];
-
- /* Initialize PCR registers for defined pads.*/
- i = 0;
- while (config->inits[i].pcr_index != -1) {
- SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
- SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value;
- i++;
- }
-}
-
-/**
- * @brief Reads a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-ioportmask_t _pal_lld_readgroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset) {
-
- (void)port;
- (void)mask;
- (void)offset;
- return 0;
-}
-
-/**
- * @brief Writes a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset,
- ioportmask_t bits) {
-
- (void)port;
- (void)mask;
- (void)offset;
- (void)bits;
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
- unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
- ioportmask_t m1 = 0x8000;
- while (m1) {
- if (mask & m1)
- SIU.PCR[pcr_index].R = mode;
- m1 >>= 1;
- ++pcr_index;
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h deleted file mode 100644 index 5304ac36d..000000000 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h +++ /dev/null @@ -1,427 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/SIUL_v1/pal_lld.h
- * @brief SPC5xx SIUL low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name SIUL-specific PAL modes
- * @{
- */
-#define PAL_SPC5_SMC (1U << 14)
-#define PAL_SPC5_APC (1U << 13)
-#define PAL_SPC5_PA_MASK (3U << 10)
-#define PAL_SPC5_PA(n) ((n) << 10)
-#define PAL_SPC5_OBE (1U << 9)
-#define PAL_SPC5_IBE (1U << 8)
-#define PAL_SPC5_ODE (1U << 5)
-#define PAL_SPC5_SRC (1U << 2)
-#define PAL_SPC5_WPE (1U << 1)
-#define PAL_SPC5_WPS (1U << 0)
-/** @} */
-
-/**
- * @name Pads mode constants
- * @{
- */
-/**
- * @brief After reset state.
- */
-#define PAL_MODE_RESET 0
-
-/**
- * @brief Safe state for <b>unconnected</b> pads.
- */
-#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS)
-
-/**
- * @brief Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT (PAL_SPC5_IBE)
-
-/**
- * @brief Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \
- PAL_SPC5_WPS)
-
-/**
- * @brief Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE)
-
-/**
- * @brief Analog input mode.
- */
-#define PAL_MODE_INPUT_ANALOG PAL_SPC5_APC
-
-/**
- * @brief Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE)
-
-/**
- * @brief Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \
- PAL_SPC5_ODE)
-
-/**
- * @brief Alternate "n" output pad.
- * @note Both the IBE and OBE bits are specified in this mask, the OBE
- * bit is not required for some PCRs but in that case it is
- * ignored.
- */
-#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \
- PAL_SPC5_PA(n))
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint16_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef uint32_t ioportid_t;
-
-/**
- * @brief SIUL register initializer type.
- */
-typedef struct {
- int32_t pcr_index;
- uint8_t gpdo_value;
- iomode_t pcr_value;
-} spc_siu_init_t;
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- iomode_t default_mode;
- const spc_siu_init_t *inits;
- const uint8_t *padsels;
-} PALConfig;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief I/O port A identifier.
- */
-#define PORT_A 0
-
-/**
- * @brief I/O port B identifier.
- */
-#define PORT_B 1
-
-/**
- * @brief I/O port C identifier.
- */
-#define PORT_C 2
-
-/**
- * @brief I/O port D identifier.
- */
-#define PORT_D 3
-
-/**
- * @brief I/O port E identifier.
- */
-#define PORT_E 4
-
-/**
- * @brief I/O port F identifier.
- */
-#define PORT_F 5
-
-/**
- * @brief I/O port G identifier.
- */
-#define PORT_G 6
-
-/**
- * @brief I/O port H identifier.
- */
-#define PORT_H 7
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Port bit helper macro.
- * @note Overrides the one in @p pal.h.
- *
- * @param[in] n bit position within the port
- *
- * @return The bit mask.
- */
-#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) \
- (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
-
-/**
- * @brief Reads a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) \
- _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief Writes a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) \
- _pal_lld_writegroup(port, mask, offset, bits)
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) \
- (SIU.GPDI[((port) * 16) + (pad)].R)
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) \
- (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = 1)
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = 0)
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- ioportmask_t _pal_lld_readgroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset);
- void _pal_lld_writegroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset,
- ioportmask_t bits);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c deleted file mode 100644 index 1d77a177a..000000000 --- a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c +++ /dev/null @@ -1,145 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/SIU_v1/pal_lld.c
- * @brief SPC5xx SIU low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if defined(SPC5_SIU_SYSTEM_PINS)
-static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief SPC5xx I/O ports configuration.
- *
- * @param[in] config the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
- unsigned i;
-
- /* Initialize PCR registers for defined pads.*/
- i = 0;
- while (config->inits[i].pcr_index != -1) {
- SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
- SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value;
- i++;
- }
-}
-
-/**
- * @brief Reads a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-ioportmask_t _pal_lld_readgroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset) {
-
- (void)port;
- (void)mask;
- (void)offset;
- return 0;
-}
-
-/**
- * @brief Writes a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset,
- ioportmask_t bits) {
-
- (void)port;
- (void)mask;
- (void)offset;
- (void)bits;
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
- unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
- ioportmask_t m1 = 0x8000;
- while (m1) {
- if (mask & m1)
- SIU.PCR[pcr_index].R = mode;
- m1 >>= 1;
- ++pcr_index;
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h deleted file mode 100644 index b9c72bf0c..000000000 --- a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h +++ /dev/null @@ -1,423 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/SIU_v1/pal_lld.h
- * @brief SPC5xx SIU low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name SIU-specific PAL modes
- * @{
- */
-#define PAL_SPC5_PA_MASK (15U << 10)
-#define PAL_SPC5_PA(n) ((n) << 10)
-#define PAL_SPC5_OBE (1U << 9)
-#define PAL_SPC5_IBE (1U << 8)
-#define PAL_SPC5_DSC_10PF (0U << 6)
-#define PAL_SPC5_DSC_20PF (1U << 6)
-#define PAL_SPC5_DSC_30PF (2U << 6)
-#define PAL_SPC5_DSC_50PF (3U << 6)
-#define PAL_SPC5_ODE (1U << 5)
-#define PAL_SPC5_HYS (1U << 4)
-#define PAL_SPC5_WPE (1U << 1)
-#define PAL_SPC5_WPS (1U << 0)
-/** @} */
-
-/**
- * @name Pads mode constants
- * @{
- */
-/**
- * @brief After reset state.
- */
-#define PAL_MODE_RESET 0
-
-/**
- * @brief Safe state for <b>unconnected</b> pads.
- */
-#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS)
-
-/**
- * @brief Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT (PAL_SPC5_IBE)
-
-/**
- * @brief Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \
- PAL_SPC5_WPS)
-
-/**
- * @brief Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE)
-
-/**
- * @brief Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE)
-
-/**
- * @brief Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \
- PAL_SPC5_ODE)
-
-/**
- * @brief Alternate "n" output pad.
- * @note Both the IBE and OBE bits are specified in this mask, the OBE
- * bit is not required for some PCRs but in that case it is
- * ignored.
- */
-#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \
- PAL_SPC5_PA(n))
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint16_t ioportmask_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef uint32_t ioportid_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief SIU/SIUL register initializer type.
- */
-typedef struct {
- int32_t pcr_index;
- uint8_t gpdo_value;
- iomode_t pcr_value;
-} spc_siu_init_t;
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- const spc_siu_init_t *inits;
-} PALConfig;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @name Port identifiers
- * @{
- */
-#define PORT0 0
-#define PORT1 1
-#define PORT2 2
-#define PORT3 3
-#define PORT4 4
-#define PORT5 5
-#define PORT6 6
-#define PORT7 7
-#define PORT8 8
-#define PORT9 9
-#define PORT10 10
-#define PORT11 11
-#define PORT12 12
-#define PORT13 13
-#define PORT14 14
-#define PORT15 15
-#define PORT16 16
-#define PORT17 17
-#define PORT18 18
-#define PORT19 19
-#define PORT20 20
-#define PORT21 21
-#define PORT22 22
-#define PORT23 23
-#define PORT24 24
-#define PORT25 25
-#define PORT26 26
-#define PORT27 27
-#define PORT28 28
-#define PORT29 29
-#define PORT30 30
-#define PORT31 31
-/** @} */
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Port bit helper macro.
- * @note Overrides the one in @p pal.h.
- *
- * @param[in] n bit position within the port
- *
- * @return The bit mask.
- */
-#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__)
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) \
- (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
-
-/**
- * @brief Reads a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) \
- _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief Writes a group of bits.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) \
- _pal_lld_writegroup(port, mask, offset, bits)
-
-#endif /* SPC5_SIU_SUPPORTS_PORTS */
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) \
- (SIU.GPDI[((port) * 16) + (pad)].R)
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) \
- (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = 1)
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = 0)
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) \
- (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- ioportmask_t _pal_lld_readgroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset);
- void _pal_lld_writegroup(ioportid_t port,
- ioportmask_t mask,
- uint_fast8_t offset,
- ioportmask_t bits);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c deleted file mode 100644 index 52337ff6b..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c +++ /dev/null @@ -1,907 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/icu_lld.c
- * @brief SPC5xx low level icu driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief ICUD1 driver identifier.
- * @note The driver ICUD1 allocates the unified channel eMIOS_CH0
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief ICUD2 driver identifier.
- * @note The driver ICUD2 allocates the unified channel eMIOS_CH1
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief ICUD3 driver identifier.
- * @note The driver ICUD3 allocates the unified channel eMIOS_CH2
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
- -
-/**
- * @brief ICUD4 driver identifier.
- * @note The driver ICUD4 allocates the unified channel eMIOS_CH3
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief ICUD5 driver identifier.
- * @note The driver ICUD5 allocates the unified channel eMIOS_CH4
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief ICUD6 driver identifier.
- * @note The driver ICUD6 allocates the unified channel eMIOS_CH5
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief ICUD7 driver identifier.
- * @note The driver ICUD7 allocates the unified channel eMIOS_CH6
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief ICUD8 driver identifier.
- * @note The driver ICUD8 allocates the unified channel eMIOS_CH8
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH8 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief ICUD9 driver identifier.
- * @note The driver ICUD9 allocates the unified channel eMIOS_CH7
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH7 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief ICUD10 driver identifier.
- * @note The driver ICUD10 allocates the unified channel eMIOS_CH16
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH16 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/**
- * @brief ICUD11 driver identifier.
- * @note The driver ICUD11 allocates the unified channel eMIOS_CH17
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH17 || defined(__DOXYGEN__)
-ICUDriver ICUD11;
-#endif
-
-/**
- * @brief ICUD12 driver identifier.
- * @note The driver ICUD12 allocates the unified channel eMIOS_CH18
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH18 || defined(__DOXYGEN__)
-ICUDriver ICUD12;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Width and Period registers.
- */
-uint32_t width;
-uint32_t period;
-
-/**
- * @brief A2 temp registers.
- */
-uint32_t A2_1, A2_2, A2_3;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief ICU IRQ handler.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-
- uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
-
- if (sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL) {
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
- _icu_isr_invoke_overflow_cb(icup);
- }
- if (sr && EMIOSS_FLAG) {
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
- if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- }
- } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- }
- }
- }
- if (sr && EMIOSS_OVR) {
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
- }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS_CH0
-#if !defined(SPC5_EMIOS_FLAG_F0_HANDLER)
-#error "SPC5_EMIOS_FLAG_F0_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 0 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F0_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH0 */
-
-#if SPC5_ICU_USE_EMIOS_CH1
-#if !defined(SPC5_EMIOS_FLAG_F1_HANDLER)
-#error "SPC5_EMIOS_FLAG_F1_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-
-#if SPC5_ICU_USE_EMIOS_CH2
-#if !defined(SPC5_EMIOS_FLAG_F2_HANDLER)
-#error "SPC5_EMIOS_FLAG_F2_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 2 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F2_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-
-#if SPC5_ICU_USE_EMIOS_CH3
-#if !defined(SPC5_EMIOS_FLAG_F3_HANDLER)
-#error "SPC5_EMIOS_FLAG_F3_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-
-#if SPC5_ICU_USE_EMIOS_CH4
-#if !defined(SPC5_EMIOS_FLAG_F4_HANDLER)
-#error "SPC5_EMIOS_FLAG_F4_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 4 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F4_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-
-#if SPC5_ICU_USE_EMIOS_CH5
-#if !defined(SPC5_EMIOS_FLAG_F5_HANDLER)
-#error "SPC5_EMIOS_FLAG_F5_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-
-#if SPC5_ICU_USE_EMIOS_CH6
-#if !defined(SPC5_EMIOS_FLAG_F6_HANDLER)
-#error "SPC5_EMIOS_FLAG_F6_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 6 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F6_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD7);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-
-#if SPC5_ICU_USE_EMIOS_CH7
-#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER)
-#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 7 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F7_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD9);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-
-#if SPC5_ICU_USE_EMIOS_CH7
-#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER)
-#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 8 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F8_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD8);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH8 */
-
-#if SPC5_ICU_USE_EMIOS_CH16
-#if !defined(SPC5_EMIOS_FLAG_F16_HANDLER)
-#error "SPC5_EMIOS_FLAG_F16_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 16 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F16_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD10);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-
-#if SPC5_ICU_USE_EMIOS_CH17
-#if !defined(SPC5_EMIOS_FLAG_F17_HANDLER)
-#error "SPC5_EMIOS_FLAG_F17_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 17 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F17_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD11);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-
-#if SPC5_ICU_USE_EMIOS_CH18
-#if !defined(SPC5_EMIOS_FLAG_F18_HANDLER)
-#error "SPC5_EMIOS_FLAG_F18_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS Channel 18 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F18_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD12);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
- /* Initialize A2 temp registers.*/
- A2_1 = 0U;
- A2_2 = 0U;
- A2_3 = 0U;
-
- /* eMIOSx channels initially all not in use.*/
- reset_emios_active_channels();
-
-#if SPC5_ICU_USE_EMIOS_CH0
- /* Driver initialization.*/
- icuObjectInit(&ICUD1);
- ICUD1.emiosp = &EMIOS;
- ICUD1.ch_number = 0U;
- ICUD1.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH0 */
-
-#if SPC5_ICU_USE_EMIOS_CH1
- /* Driver initialization.*/
- icuObjectInit(&ICUD2);
- ICUD2.emiosp = &EMIOS;
- ICUD2.ch_number = 1U;
- ICUD2.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-
-#if SPC5_ICU_USE_EMIOS_CH2
- /* Driver initialization.*/
- icuObjectInit(&ICUD3);
- ICUD3.emiosp = &EMIOS;
- ICUD3.ch_number = 2U;
- ICUD3.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-
-#if SPC5_ICU_USE_EMIOS_CH3
- /* Driver initialization.*/
- icuObjectInit(&ICUD4);
- ICUD4.emiosp = &EMIOS;
- ICUD4.ch_number = 3U;
- ICUD4.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-
-#if SPC5_ICU_USE_EMIOS_CH4
- /* Driver initialization.*/
- icuObjectInit(&ICUD5);
- ICUD5.emiosp = &EMIOS;
- ICUD5.ch_number = 4U;
- ICUD5.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-
-#if SPC5_ICU_USE_EMIOS_CH5
- /* Driver initialization.*/
- icuObjectInit(&ICUD6);
- ICUD6.emiosp = &EMIOS;
- ICUD6.ch_number = 5U;
- ICUD6.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-
-#if SPC5_ICU_USE_EMIOS_CH6
- /* Driver initialization.*/
- icuObjectInit(&ICUD7);
- ICUD7.emiosp = &EMIOS;
- ICUD7.ch_number = 6U;
- ICUD7.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-
-#if SPC5_ICU_USE_EMIOS_CH8
- /* Driver initialization.*/
- icuObjectInit(&ICUD8);
- ICUD8.emiosp = &EMIOS;
- ICUD8.ch_number = 8U;
- ICUD8.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH8 */
-
-#if SPC5_ICU_USE_EMIOS_CH7
- /* Driver initialization.*/
- icuObjectInit(&ICUD9);
- ICUD9.emiosp = &EMIOS;
- ICUD9.ch_number = 7U;
- ICUD9.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-
-#if SPC5_ICU_USE_EMIOS_CH16
- /* Driver initialization.*/
- icuObjectInit(&ICUD10);
- ICUD10.emiosp = &EMIOS;
- ICUD10.ch_number = 16U;
- ICUD10.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-
-#if SPC5_ICU_USE_EMIOS_CH17
- /* Driver initialization.*/
- icuObjectInit(&ICUD11);
- ICUD11.emiosp = &EMIOS;
- ICUD11.ch_number = 17U;
- ICUD11.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-
-#if SPC5_ICU_USE_EMIOS_CH18
- /* Driver initialization.*/
- icuObjectInit(&ICUD12);
- ICUD12.emiosp = &EMIOS;
- ICUD12.ch_number = 18U;
- ICUD12.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-
-#if SPC5_ICU_USE_EMIOS
-
-#if SPC5_EMIOS_NUM_CHANNELS == 16
- INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
- INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F7_NUMBER].R = SPC5_EMIOS_FLAG_F7_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F16_NUMBER].R = SPC5_EMIOS_FLAG_F16_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F17_NUMBER].R = SPC5_EMIOS_FLAG_F17_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F18_NUMBER].R = SPC5_EMIOS_FLAG_F18_PRIORITY;
-#endif
-
-#endif
-}
-
-/**
- * @brief Configures and activates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
- chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
- "icu_lld_start(), #1", "too many channels");
-
- if (icup->state == ICU_STOP) {
- /* Enables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS_CH0
- if (&ICUD1 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH0 */
-#if SPC5_ICU_USE_EMIOS_CH1
- if (&ICUD2 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-#if SPC5_ICU_USE_EMIOS_CH2
- if (&ICUD3 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-#if SPC5_ICU_USE_EMIOS_CH3
- if (&ICUD4 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-#if SPC5_ICU_USE_EMIOS_CH4
- if (&ICUD5 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-#if SPC5_ICU_USE_EMIOS_CH5
- if (&ICUD6 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-#if SPC5_ICU_USE_EMIOS_CH6
- if (&ICUD7 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-#if SPC5_ICU_USE_EMIOS_CH8
- if (&ICUD8 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH8 */
-#if SPC5_ICU_USE_EMIOS_CH7
- if (&ICUD9 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-#if SPC5_ICU_USE_EMIOS_CH16
- if (&ICUD10 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-#if SPC5_ICU_USE_EMIOS_CH17
- if (&ICUD11 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-#if SPC5_ICU_USE_EMIOS_CH18
- if (&ICUD12 == icup)
- increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-
- /* Set eMIOS Clock.*/
-#if SPC5_ICU_USE_EMIOS
- active_emios_clock(icup, NULL);
-#endif
-
- }
- /* Configures the peripheral.*/
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Set clock prescaler and control register.*/
- uint32_t psc = (icup->clock / icup->config->frequency);
- chDbgAssert((psc <= 4) &&
- ((psc * icup->config->frequency) == icup->clock) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "icu_lld_start(), #1", "invalid frequency");
-
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPREN = 0;
- icup->emiosp->CH[icup->ch_number].CCR.R |=
- EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
- EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
-
- /* Set source polarity.*/
- if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
- } else {
- icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
- }
-
- /* Direct pointers to the period and width registers in order to make
- reading data faster from within callbacks.*/
- icup->pccrp = .
- icup->wccrp = &width;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-/**
- * @brief Deactivates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
- chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
- "icu_lld_stop(), #1", "too many channels");
-
- if (icup->state == ICU_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS_CH0
- if (&ICUD1 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH0 */
-#if SPC5_ICU_USE_EMIOS_CH1
- if (&ICUD2 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-#if SPC5_ICU_USE_EMIOS_CH2
- if (&ICUD3 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-#if SPC5_ICU_USE_EMIOS_CH3
- if (&ICUD4 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-#if SPC5_ICU_USE_EMIOS_CH4
- if (&ICUD5 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-#if SPC5_ICU_USE_EMIOS_CH5
- if (&ICUD6 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-#if SPC5_ICU_USE_EMIOS_CH6
- if (&ICUD7 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-#if SPC5_ICU_USE_EMIOS_CH8
- if (&ICUD8 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH8 */
-#if SPC5_ICU_USE_EMIOS_CH7
- if (&ICUD9 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-#if SPC5_ICU_USE_EMIOS_CH16
- if (&ICUD10 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-#if SPC5_ICU_USE_EMIOS_CH17
- if (&ICUD11 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-#if SPC5_ICU_USE_EMIOS_CH18
- if (&ICUD12 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-
- /* eMIOS clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS
- deactive_emios_clock();
-#endif
-
- }
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Active interrupts.*/
- if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \
- icup->config->overflow_cb != NULL) {
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
- }
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h deleted file mode 100644 index 1a1d24c3f..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h +++ /dev/null @@ -1,443 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/icu_lld.h
- * @brief SPC5xx low level icu driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH0 FALSE
-#endif
-
-/**
- * @brief ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH1 FALSE
-#endif
-
-/**
- * @brief ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH2 FALSE
-#endif
-
-/**
- * @brief ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH3 FALSE
-#endif
-
-/**
- * @brief ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH4 FALSE
-#endif
-
-/**
- * @brief ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH5 FALSE
-#endif
-
-/**
- * @brief ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH6 FALSE
-#endif
-
-/**
- * @brief ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH8) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH8 FALSE
-#endif
-
-/**
- * @brief ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH7 FALSE
-#endif
-
-/**
- * @brief ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH16) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH16 FALSE
-#endif
-
-/**
- * @brief ICUD11 driver enable switch.
- * @details If set to @p TRUE the support for ICUD11 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH17) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH17 FALSE
-#endif
-
-/**
- * @brief ICUD12 driver enable switch.
- * @details If set to @p TRUE the support for ICUD12 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH18) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH18 FALSE
-#endif
-
-/**
- * @brief ICUD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F0_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F1_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F2_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F3_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F4_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F4_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F5_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD7 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F6_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F6_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F8_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F8_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F7_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F16_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F16_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD11 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F17_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD12 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F18_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F18_PRIORITY 7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS
-#error "EMIOS not present in the selected device"
-#endif
-
-#define SPC5_ICU_USE_EMIOS (SPC5_ICU_USE_EMIOS_CH0 || \
- SPC5_ICU_USE_EMIOS_CH1 || \
- SPC5_ICU_USE_EMIOS_CH2 || \
- SPC5_ICU_USE_EMIOS_CH3 || \
- SPC5_ICU_USE_EMIOS_CH4 || \
- SPC5_ICU_USE_EMIOS_CH5 || \
- SPC5_ICU_USE_EMIOS_CH6 || \
- SPC5_ICU_USE_EMIOS_CH7 || \
- SPC5_ICU_USE_EMIOS_CH8 || \
- SPC5_ICU_USE_EMIOS_CH16 || \
- SPC5_ICU_USE_EMIOS_CH17 || \
- SPC5_ICU_USE_EMIOS_CH18)
-
-#if !SPC5_ICU_USE_EMIOS
-#error "ICU driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
- ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
- ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
-} icumode_t;
-
-/**
- * @brief ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief ICU counter type.
- */
-typedef uint32_t icucnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Driver mode.
- */
- icumode_t mode;
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- icufreq_t frequency;
- /**
- * @brief Callback for pulse width measurement.
- */
- icucallback_t width_cb;
- /**
- * @brief Callback for cycle period measurement.
- */
- icucallback_t period_cb;
- /**
- * @brief Callback for timer overflow.
- */
- icucallback_t overflow_cb;
- /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief Structure representing an ICU driver.
- */
-struct ICUDriver {
- /**
- * @brief Driver state.
- */
- icustate_t state;
- /**
- * @brief eMIOSx channel number.
- */
- uint32_t ch_number;
- /**
- * @brief Current configuration data.
- */
- const ICUConfig *config;
- /**
- * @brief CH Counter clock.
- */
- uint32_t clock;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
- /**
- * @brief CCR register used for width capture.
- */
- volatile vuint32_t *wccrp;
- /**
- * @brief CCR register used for period capture.
- */
- volatile vuint32_t *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- * edge and the stop edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- * edge and the next start edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS_CH0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH8 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH16 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH17 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD11;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH18 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD12;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void icu_lld_init(void);
- void icu_lld_start(ICUDriver *icup);
- void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c deleted file mode 100644 index b5538f60c..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c +++ /dev/null @@ -1,951 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/pwm_lld.c
- * @brief SPC5xx low level pwm driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the unified channel EMIOS_CH9
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH9 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the unified channel EMIOS_CH10
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH10 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the unified channel EMIOS_CH11
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH11 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief PWMD4 driver identifier.
- * @note The driver PWMD4 allocates the unified channel EMIOS_CH12
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH12 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief PWMD5 driver identifier.
- * @note The driver PWMD5 allocates the unified channel EMIOS_CH13
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH13 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/**
- * @brief PWMD6 driver identifier.
- * @note The driver PWMD6 allocates the unified channel EMIOS_CH14
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH14 || defined(__DOXYGEN__)
-PWMDriver PWMD6;
-#endif
-
-/**
- * @brief PWMD7 driver identifier.
- * @note The driver PWMD7 allocates the unified channel EMIOS_CH15
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH15 || defined(__DOXYGEN__)
-PWMDriver PWMD7;
-#endif
-
-/**
- * @brief PWMD8 driver identifier.
- * @note The driver PWMD8 allocates the unified channel EMIOS_CH23
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH23 || defined(__DOXYGEN__)
-PWMDriver PWMD8;
-#endif
-
-/**
- * @brief PWMD9 driver identifier.
- * @note The driver PWMD9 allocates the unified channel EMIOS_CH19
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH19 || defined(__DOXYGEN__)
-PWMDriver PWMD9;
-#endif
-
-/**
- * @brief PWMD10 driver identifier.
- * @note The driver PWMD10 allocates the unified channel EMIOS_CH20
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH20 || defined(__DOXYGEN__)
-PWMDriver PWMD10;
-#endif
-
-/**
- * @brief PWMD11 driver identifier.
- * @note The driver PWMD11 allocates the unified channel EMIOS_CH21
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH21 || defined(__DOXYGEN__)
-PWMDriver PWMD11;
-#endif
-
-/**
- * @brief PWMD12 driver identifier.
- * @note The driver PWMD12 allocates the unified channel EMIOS_CH22
- * when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH22 || defined(__DOXYGEN__)
-PWMDriver PWMD12;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief PWM IRQ handler.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-
- uint32_t sr = pwmp->emiosp->CH[pwmp->ch_number].CSR.R;
-
- if (sr && EMIOSS_OVFL) {
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVFLC;
- }
- if (sr && EMIOSS_OVR) {
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVRC;
- }
- if (sr && EMIOSS_FLAG) {
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_FLAGC;
-
- if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
- if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \
- pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \
- pwmp->config->channels[0].callback != NULL) {
- pwmp->config->channels[0].callback(pwmp);
- }
- } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
- if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \
- pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \
- pwmp->config->channels[0].callback != NULL) {
- pwmp->config->channels[0].callback(pwmp);
- }
- }
- }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS_CH9
-#if !defined(SPC5_EMIOS_FLAG_F9_HANDLER)
-#error "SPC5_EMIOS_FLAG_F9_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F9_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
-#if !defined(SPC5_EMIOS_FLAG_F10_HANDLER)
-#error "SPC5_EMIOS_FLAG_F10_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 10 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F10_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH11
-#if !defined(SPC5_EMIOS_FLAG_F11_HANDLER)
-#error "SPC5_EMIOS_FLAG_F11_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 11 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH11 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
-#if !defined(SPC5_EMIOS_FLAG_F12_HANDLER)
-#error "SPC5_EMIOS_FLAG_F12_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 12 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F12_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH13
-#if !defined(SPC5_EMIOS_FLAG_F13_HANDLER)
-#error "SPC5_EMIOS_FLAG_F13_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 13 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F13_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH13 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
-#if !defined(SPC5_EMIOS_FLAG_F14_HANDLER)
-#error "SPC5_EMIOS_FLAG_F14_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 14 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F14_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
-#if !defined(SPC5_EMIOS_FLAG_F15_HANDLER)
-#error "SPC5_EMIOS_FLAG_F15_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 15 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD7);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH19
-#if !defined(SPC5_EMIOS_FLAG_F19_HANDLER)
-#error "SPC5_EMIOS_FLAG_F19_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 19 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F19_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD9);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
-#if !defined(SPC5_EMIOS_FLAG_F20_HANDLER)
-#error "SPC5_EMIOS_FLAG_F20_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 20 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F20_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD10);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
-#if !defined(SPC5_EMIOS_FLAG_F21_HANDLER)
-#error "SPC5_EMIOS_FLAG_F21_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 21 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F21_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD11);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
-#if !defined(SPC5_EMIOS_FLAG_F22_HANDLER)
-#error "SPC5_EMIOS_FLAG_F22_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 22 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F22_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD12);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
-#if !defined(SPC5_EMIOS_FLAG_F23_HANDLER)
-#error "SPC5_EMIOS_FLAG_F23_HANDLER not defined"
-#endif
-/**
- * @brief EMIOS Channel 23 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F23_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- pwm_lld_serve_interrupt(&PWMD8);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
- /* eMIOSx channels initially all not in use.*/
- reset_emios_active_channels();
-
-#if SPC5_PWM_USE_EMIOS_CH9
- /* Driver initialization.*/
- pwmObjectInit(&PWMD1);
- PWMD1.emiosp = &EMIOS;
- PWMD1.ch_number = 9U;
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
- /* Driver initialization.*/
- pwmObjectInit(&PWMD2);
- PWMD2.emiosp = &EMIOS;
- PWMD2.ch_number = 10U;
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH11
- /* Driver initialization.*/
- pwmObjectInit(&PWMD3);
- PWMD3.emiosp = &EMIOS;
- PWMD3.ch_number = 11U;
-#endif /* SPC5_PWM_USE_EMIOS_CH11 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
- /* Driver initialization.*/
- pwmObjectInit(&PWMD4);
- PWMD4.emiosp = &EMIOS;
- PWMD4.ch_number = 12U;
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH13
- /* Driver initialization.*/
- pwmObjectInit(&PWMD5);
- PWMD5.emiosp = &EMIOS;
- PWMD5.ch_number = 13U;
-#endif /* SPC5_PWM_USE_EMIOS_CH13 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
- /* Driver initialization.*/
- pwmObjectInit(&PWMD6);
- PWMD6.emiosp = &EMIOS;
- PWMD6.ch_number = 14U;
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
- /* Driver initialization.*/
- pwmObjectInit(&PWMD7);
- PWMD7.emiosp = &EMIOS;
- PWMD7.ch_number = 15U;
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
- /* Driver initialization.*/
- pwmObjectInit(&PWMD8);
- PWMD8.emiosp = &EMIOS;
- PWMD8.ch_number = 23U;
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_PWM_USE_EMIOS_CH19
- /* Driver initialization.*/
- pwmObjectInit(&PWMD9);
- PWMD9.emiosp = &EMIOS;
- PWMD9.ch_number = 19U;
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
- /* Driver initialization.*/
- pwmObjectInit(&PWMD10);
- PWMD10.emiosp = &EMIOS;
- PWMD10.ch_number = 20U;
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
- /* Driver initialization.*/
- pwmObjectInit(&PWMD11);
- PWMD11.emiosp = &EMIOS;
- PWMD11.ch_number = 21U;
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
- /* Driver initialization.*/
- pwmObjectInit(&PWMD12);
- PWMD12.emiosp = &EMIOS;
- PWMD12.ch_number = 22U;
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-
-#if SPC5_PWM_USE_EMIOS
-
-#if SPC5_EMIOS_NUM_CHANNELS == 16
- INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
- INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F19_NUMBER].R = SPC5_EMIOS_FLAG_F19_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F20_NUMBER].R = SPC5_EMIOS_FLAG_F20_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F21_NUMBER].R = SPC5_EMIOS_FLAG_F21_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F22_NUMBER].R = SPC5_EMIOS_FLAG_F22_PRIORITY;
- INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
-#endif
-
-#endif
-
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
- uint32_t psc = 0;
-
- chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
- "pwm_lld_start(), #1", "too many channels");
-
- if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_EMIOS_CH9
- if (&PWMD1 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
- if (&PWMD2 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH11
- if (&PWMD3 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH11 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
- if (&PWMD4 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH13
- if (&PWMD5 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH13 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
- if (&PWMD6 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
- if (&PWMD7 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
- if (&PWMD8 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_PWM_USE_EMIOS_CH19
- if (&PWMD9 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
- if (&PWMD10 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
- if (&PWMD11 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
- if (&PWMD12 == pwmp) {
- increase_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-
- /* Set eMIOS Clock.*/
-#if SPC5_PWM_USE_EMIOS
- active_emios_clock(NULL, pwmp);
-#endif
-
- }
- /* Configures the peripheral.*/
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Set clock prescaler and control register.*/
- psc = (SPC5_EMIOS_CLK / pwmp->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_EMIOS_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "pwm_lld_start(), #1", "invalid frequency");
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 0;
- pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 1U;
- pwmp->emiosp->CH[pwmp->ch_number].CCNTR.R = 1U;
- pwmp->emiosp->CH[pwmp->ch_number].CADR.R = 0U;
- pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = pwmp->config->period;
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R |=
- EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | EMIOS_CCR_MODE_OPWFMB | 2U;
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_UCPREN;
-
- /* Set output polarity.*/
- if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_EDPOL;
- } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R &= ~EMIOSC_EDPOL;
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
-
- } else if (pwmp->config->mode == PWM_ALIGN_CENTER) {
- /* Not implemented.*/
- }
-
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
- "pwm_lld_stop(), #1", "too many channels");
-
- if (pwmp->state == PWM_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_PWM_USE_EMIOS_CH9
- if (&PWMD1 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
- if (&PWMD2 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH11
- if (&PWMD3 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH11 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
- if (&PWMD4 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH13
- if (&PWMD5 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH13 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
- if (&PWMD6 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
- if (&PWMD7 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
- if (&PWMD8 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_PWM_USE_EMIOS_CH19
- if (&PWMD9 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
- if (&PWMD10 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
- if (&PWMD11 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
- if (&PWMD12 == pwmp) {
- /* Reset UC Control Register.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
- decrease_emios_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-
- /* eMIOS clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS
- deactive_emios_clock();
-#endif
-
- }
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
- pwmp->period = period;
- pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = period;
-
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-
- (void)channel;
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Set pwm width.*/
- pwmp->emiosp->CH[pwmp->ch_number].CADR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL || \
- pwmp->config->channels[0].callback != NULL) {
- pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 1U;
- }
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
-
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- (void)channel;
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 0;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h deleted file mode 100644 index fa7417844..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h +++ /dev/null @@ -1,457 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/pwm_lld.h
- * @brief SPC5xx low level pwm driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 1
-
-/**
- * @brief Edge-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE 0x00
-
-/**
- * @brief Center-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER 0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH9) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH9 FALSE
-#endif
-
-/**
- * @brief PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH10) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH10 FALSE
-#endif
-
-/**
- * @brief PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH11) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH11 FALSE
-#endif
-
-/**
- * @brief PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH12) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH12 FALSE
-#endif
-
-/**
- * @brief PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH13) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH13 FALSE
-#endif
-
-/**
- * @brief PWMD6 driver enable switch.
- * @details If set to @p TRUE the support for PWMD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH14) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH14 FALSE
-#endif
-
-/**
- * @brief PWMD7 driver enable switch.
- * @details If set to @p TRUE the support for PWMD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH15) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH15 FALSE
-#endif
-
-/**
- * @brief PWMD8 driver enable switch.
- * @details If set to @p TRUE the support for PWMD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH23) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH23 FALSE
-#endif
-
-/**
- * @brief PWMD9 driver enable switch.
- * @details If set to @p TRUE the support for PWMD9 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH19) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH19 FALSE
-#endif
-
-/**
- * @brief PWMD10 driver enable switch.
- * @details If set to @p TRUE the support for PWMD10 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH20) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH20 FALSE
-#endif
-
-/**
- * @brief PWMD11 driver enable switch.
- * @details If set to @p TRUE the support for PWMD11 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH21) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH21 FALSE
-#endif
-
-/**
- * @brief PWMD12 driver enable switch.
- * @details If set to @p TRUE the support for PWMD12 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH22) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH22 FALSE
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F9_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F10_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F10_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F11_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F12_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F12_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F13_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F14_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F14_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD7 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F15_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F23_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F19_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F20_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F20_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD11 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F21_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD12 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F22_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F22_PRIORITY 7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS
-#error "EMIOS not present in the selected device"
-#endif
-
-#define SPC5_PWM_USE_EMIOS (SPC5_PWM_USE_EMIOS_CH9 || \
- SPC5_PWM_USE_EMIOS_CH10 || \
- SPC5_PWM_USE_EMIOS_CH11 || \
- SPC5_PWM_USE_EMIOS_CH12 || \
- SPC5_PWM_USE_EMIOS_CH13 || \
- SPC5_PWM_USE_EMIOS_CH14 || \
- SPC5_PWM_USE_EMIOS_CH15 || \
- SPC5_PWM_USE_EMIOS_CH19 || \
- SPC5_PWM_USE_EMIOS_CH20 || \
- SPC5_PWM_USE_EMIOS_CH21 || \
- SPC5_PWM_USE_EMIOS_CH22 || \
- SPC5_PWM_USE_EMIOS_CH23)
-
-#if !SPC5_PWM_USE_EMIOS
-#error "PWM driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief PWM counter type.
- */
-typedef uint32_t pwmcnt_t;
-
-/**
- * @brief PWM driver channel configuration structure.
- * @note Some architectures may not be able to support the channel mode
- * or the callback, in this case the fields are ignored.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
- /**
- * @brief PWM functional mode.
- */
- pwmmode_t mode;
-} PWMConfig;
-
-/**
- * @brief Structure representing an PWM driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief eMIOSx channel number.
- */
- uint8_t ch_number;
- /**
- * @brief Current configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS_CH9 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH10 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH11 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH12 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH13 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH14 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD6;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH15 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD7;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH23 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD8;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH19 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD9;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH20 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD10;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH21 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD11;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH22 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD12;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c deleted file mode 100644 index 0533b50e3..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c +++ /dev/null @@ -1,117 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/spc5_emios.c
- * @brief eMIOS200 helper driver code.
- *
- * @addtogroup SPC5xx_eMIOS200
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active eMIOSx Channels.
- */
-static uint32_t emios_active_channels;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-void reset_emios_active_channels() {
- emios_active_channels = 0;
-}
-
-uint32_t get_emios_active_channels() {
- return emios_active_channels;
-}
-
-void increase_emios_active_channels() {
- emios_active_channels++;
-}
-
-void decrease_emios_active_channels() {
- emios_active_channels--;
-}
-
-void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If this is the first Channel activated then the eMIOS0 is enabled.*/
- if (emios_active_channels == 1) {
- SPC5_EMIOS_ENABLE_CLOCK();
-
- /* Disable all unified channels.*/
- if (icup != NULL) {
- icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
-
- icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- } else if (pwmp != NULL) {
- pwmp->emiosp->MCR.B.GPREN = 0;
- pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
- pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- pwmp->emiosp->MCR.B.GTBE = 1U;
-
- pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- }
-
- }
-}
-
-void deactive_emios_clock() {
- /* If it is the last active channels then the eMIOS0 is disabled.*/
- if (emios_active_channels == 0) {
- SPC5_EMIOS_DISABLE_CLOCK();
-
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h deleted file mode 100644 index 97bff1ce9..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h +++ /dev/null @@ -1,115 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/eMIOS200_v1/spc5_emios.h
- * @brief eMIOS200 helper driver header.
- *
- * @addtogroup SPC5xx_eMIOS200
- * @{
- */
-
-#ifndef _SPC5_EMIOS_H_
-#define _SPC5_EMIOS_H_
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define EMIOSMCR_MDIS (1 << 30)
-#define EMIOSMCR_FRZ (1 << 29)
-#define EMIOSMCR_GTBE (1 << 28)
-#define EMIOSMCR_GPREN (1 << 26)
-#define EMIOSMCR_GPRE(n) ((n) << 8)
-
-#define EMIOSC_FREN (1 << 31)
-#define EMIOSC_UCPRE(n) ((n) << 26)
-#define EMIOSC_UCPREN (1 << 25)
-#define EMIOSC_DMA (1 << 24)
-#define EMIOSC_IF(n) ((n) << 19)
-#define EMIOSC_FCK (1 << 18)
-#define EMIOSC_FEN (1 << 17)
-#define EMIOSC_FORCMA (1 << 13)
-#define EMIOSC_FORCMB (1 << 12)
-#define EMIOSC_BSL(n) ((n) << 9)
-#define EMIOSC_EDSEL (1 << 8)
-#define EMIOSC_EDPOL (1 << 7)
-#define EMIOSC_MODE(n) ((n) << 0)
-
-#define EMIOS_BSL_COUNTER_BUS_A 0
-#define EMIOS_BSL_COUNTER_BUS_2 1
-#define EMIOS_BSL_INTERNAL_COUNTER 3
-
-#define EMIOS_CCR_MODE_GPIO_IN 0
-#define EMIOS_CCR_MODE_GPIO_OUT 1
-#define EMIOS_CCR_MODE_SAIC 2
-#define EMIOS_CCR_MODE_SAOC 3
-#define EMIOS_CCR_MODE_IPWM 4
-#define EMIOS_CCR_MODE_IPM 5
-#define EMIOS_CCR_MODE_DAOC_B_MATCH 6
-#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7
-#define EMIOS_CCR_MODE_MC_CMS 16
-#define EMIOS_CCR_MODE_MC_CME 17
-#define EMIOS_CCR_MODE_MC_UP_DOWN 18
-#define EMIOS_CCR_MODE_OPWMT 38
-#define EMIOS_CCR_MODE_MCB_UP 80
-#define EMIOS_CCR_MODE_MCB_UP_DOWN 84
-#define EMIOS_CCR_MODE_OPWFMB 88
-#define EMIOS_CCR_MODE_OPWMCB_TE 92
-#define EMIOS_CCR_MODE_OPWMCB_LE 93
-#define EMIOS_CCR_MODE_OPWMB 96
-
-#define EMIOSS_OVR (1 << 31)
-#define EMIOSS_OVRC (1 << 31)
-#define EMIOSS_OVFL (1 << 15)
-#define EMIOSS_OVFLC (1 << 15)
-#define EMIOSS_FLAG (1 << 0)
-#define EMIOSS_FLAGC (1 << 0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-void reset_emios_active_channels(void);
-uint32_t get_emios_active_channels(void);;
-void increase_emios_active_channels(void);
-void decrease_emios_active_channels(void);
-void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios_clock(void);
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-#endif /* _SPC5_EMIOS_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c deleted file mode 100644 index a8167c69c..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c +++ /dev/null @@ -1,783 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/icu_lld.c
- * @brief SPC5xx low level ICU driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief ICUD1 driver identifier.
- * @note The driver ICUD1 allocates the unified channel eMIOS0_CH0
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief ICUD2 driver identifier.
- * @note The driver ICUD2 allocates the unified channel eMIOS0_CH1
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief ICUD3 driver identifier.
- * @note The driver ICUD3 allocates the unified channel eMIOS0_CH2
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief ICUD4 driver identifier.
- * @note The driver ICUD4 allocates the unified channel eMIOS0_CH3
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief ICUD5 driver identifier.
- * @note The driver ICUD5 allocates the unified channel eMIOS0_CH4
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief ICUD6 driver identifier.
- * @note The driver ICUD6 allocates the unified channel eMIOS0_CH5
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief ICUD7 driver identifier.
- * @note The driver ICUD7 allocates the unified channel eMIOS0_CH6
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief ICUD8 driver identifier.
- * @note The driver ICUD8 allocates the unified channel eMIOS0_CH7
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH7 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief ICUD9 driver identifier.
- * @note The driver ICUD9 allocates the unified channel eMIOS0_CH24
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief ICUD10 driver identifier.
- * @note The driver ICUD10 allocates the unified channel eMIOS1_CH24
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS1_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Width and Period registers.
- */
-int16_t width;
-int16_t period;
-
-/**
- * @brief A2 temp registers.
- */
-uint16_t A2_1, A2_2, A2_3;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief ICU IRQ handler.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
- uint32_t gfr = icup->emiosp->GFR.R;
-
- if (gfr && (1 << icup->ch_number)) {
- uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
-
- if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
- _icu_isr_invoke_overflow_cb(icup);
- }
- if (sr && EMIOSS_FLAG){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
- if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- }
- } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- }
- }
- }
- if(sr && EMIOSS_OVR){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
- }
-
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1
-#if !defined(SPC5_EMIOS0_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS0_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 0 and 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F0F1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
- icu_lld_serve_interrupt(&ICUD1);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1
- icu_lld_serve_interrupt(&ICUD2);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3
-#if !defined(SPC5_EMIOS0_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS0_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 2 and 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F2F3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH2
- icu_lld_serve_interrupt(&ICUD3);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3
- icu_lld_serve_interrupt(&ICUD4);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5
-#if !defined(SPC5_EMIOS0_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS0_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 4 and 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F4F5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH4
- icu_lld_serve_interrupt(&ICUD5);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5
- icu_lld_serve_interrupt(&ICUD6);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7
-
-#if !defined(SPC5_EMIOS0_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS0_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 6 and 7 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F6F7_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH6
- icu_lld_serve_interrupt(&ICUD7);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7
- icu_lld_serve_interrupt(&ICUD8);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
-#if !defined(SPC5_EMIOS0_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS0_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 24 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F24F25_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH24
- icu_lld_serve_interrupt(&ICUD9);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
-#if !defined(SPC5_EMIOS1_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS1_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 24 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F24F25_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS1_CH24
- icu_lld_serve_interrupt(&ICUD10);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
- /* Initialize A2 temp registers.*/
- A2_1 = 0U;
- A2_2 = 0U;
- A2_3 = 0U;
-
- /* eMIOSx channels initially all not in use.*/
- reset_emios0_active_channels();
- reset_emios1_active_channels();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
- /* Driver initialization.*/
- icuObjectInit(&ICUD1);
- ICUD1.emiosp = &EMIOS_0;
- ICUD1.ch_number = 0U;
- ICUD1.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-
-#if SPC5_ICU_USE_EMIOS0_CH1
- /* Driver initialization.*/
- icuObjectInit(&ICUD2);
- ICUD2.emiosp = &EMIOS_0;
- ICUD2.ch_number = 1U;
- ICUD2.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2
- /* Driver initialization.*/
- icuObjectInit(&ICUD3);
- ICUD3.emiosp = &EMIOS_0;
- ICUD3.ch_number = 2U;
- ICUD3.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-
-#if SPC5_ICU_USE_EMIOS0_CH3
- /* Driver initialization.*/
- icuObjectInit(&ICUD4);
- ICUD4.emiosp = &EMIOS_0;
- ICUD4.ch_number = 3U;
- ICUD4.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4
- /* Driver initialization.*/
- icuObjectInit(&ICUD5);
- ICUD5.emiosp = &EMIOS_0;
- ICUD5.ch_number = 4U;
- ICUD5.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-
-#if SPC5_ICU_USE_EMIOS0_CH5
- /* Driver initialization.*/
- icuObjectInit(&ICUD6);
- ICUD6.emiosp = &EMIOS_0;
- ICUD6.ch_number = 5U;
- ICUD6.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6
- /* Driver initialization.*/
- icuObjectInit(&ICUD7);
- ICUD7.emiosp = &EMIOS_0;
- ICUD7.ch_number = 6U;
- ICUD7.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-
-#if SPC5_ICU_USE_EMIOS0_CH7
- /* Driver initialization.*/
- icuObjectInit(&ICUD8);
- ICUD8.emiosp = &EMIOS_0;
- ICUD8.ch_number = 7U;
- ICUD8.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
- /* Driver initialization.*/
- icuObjectInit(&ICUD9);
- ICUD9.emiosp = &EMIOS_0;
- ICUD9.ch_number = 24U;
- ICUD9.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
- /* Driver initialization.*/
- icuObjectInit(&ICUD10);
- ICUD10.emiosp = &EMIOS_1;
- ICUD10.ch_number = 24U;
- ICUD10.clock = SPC5_EMIOS1_CLK;
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-#if SPC5_ICU_USE_EMIOS0
-
- INTC.PSR[SPC5_EMIOS0_GFR_F0F1_NUMBER].R = SPC5_EMIOS0_GFR_F0F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F2F3_NUMBER].R = SPC5_EMIOS0_GFR_F2F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F4F5_NUMBER].R = SPC5_EMIOS0_GFR_F4F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F6F7_NUMBER].R = SPC5_EMIOS0_GFR_F6F7_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F24F25_NUMBER].R = SPC5_EMIOS0_GFR_F24F25_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_EMIOS1
-
- INTC.PSR[SPC5_EMIOS1_GFR_F24F25_NUMBER].R = SPC5_EMIOS1_GFR_F24F25_PRIORITY;
-
-#endif
-}
-
-/**
- * @brief Configures and activates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
- //uint32_t emios0_active_channels = get_emios0_active_channels();
- //uint32_t emios1_active_channels = get_emios1_active_channels();
-
- chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
- "too many channels");
-
- chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2",
- "too many channels");
-
- if (icup->state == ICU_STOP) {
- /* Enables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
- if (&ICUD1 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
- if (&ICUD2 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
- if (&ICUD3 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
- if (&ICUD4 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
- if (&ICUD5 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
- if (&ICUD6 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
- if (&ICUD7 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
- if (&ICUD8 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
- if (&ICUD9 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
- if (&ICUD10 == icup)
- increase_emios1_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
- /* Set eMIOS0 Clock.*/
-#if SPC5_ICU_USE_EMIOS0
- active_emios0_clock(icup, NULL);
-#endif
-
- /* Set eMIOS1 Clock.*/
-#if SPC5_ICU_USE_EMIOS1
- active_emios1_clock(icup, NULL);
-#endif
-
- }
- /* Configures the peripheral.*/
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Set clock prescaler and control register.*/
- uint32_t psc = (icup->clock / icup->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * icup->config->frequency) == icup->clock) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "icu_lld_start(), #1", "invalid frequency");
-
- //icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
- icup->emiosp->CH[icup->ch_number].CCR.R |=
- EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
- EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
- /*
- if (icup->emiosp == &EMIOS_0) {
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- } else if (icup->emiosp == &EMIOS_1) {
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- }
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
- */
-
- /* Set source polarity.*/
- if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
- } else {
- icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
- }
-
- /* Direct pointers to the period and width registers in order to make
- reading data faster from within callbacks.*/
- icup->pccrp = .
- icup->wccrp = &width;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-/**
- * @brief Deactivates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
- //uint32_t emios0_active_channels = get_emios0_active_channels();
- //uint32_t emios1_active_channels = get_emios1_active_channels();
-
- chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
- "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
- "too many channels");
-
- if (icup->state == ICU_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
- if (&ICUD1 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
- if (&ICUD2 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
- if (&ICUD3 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
- if (&ICUD4 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
- if (&ICUD5 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
- if (&ICUD6 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
- if (&ICUD7 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
- if (&ICUD8 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
- if (&ICUD9 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
- if (&ICUD10 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
- /* eMIOS0 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS0
- deactive_emios0_clock(icup, NULL);
-#endif
-
- /* eMIOS1 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS1
- deactive_emios1_clock(icup, NULL);
-#endif
- }
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
- /* Channel enables.*/
- /*
- if (!(icup->emiosp->UCDIS.R && (1 << icup->ch_number))) {
-
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
- }
- */
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Active interrupts.*/
- if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \
- icup->config->overflow_cb != NULL) {
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
- }
-
-
-
- /* Enable Global Time Base.*/
- /*
- if (icup->emiosp->MCR.B.GTBE == 0) {
- icup->emiosp->MCR.B.GTBE = 1U;
- }
- */
-
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h deleted file mode 100644 index 31921333c..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h +++ /dev/null @@ -1,382 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/icu_lld.h
- * @brief SPC5xx low level ICU driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH0 FALSE
-#endif
-
-/**
- * @brief ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH1 FALSE
-#endif
-
-/**
- * @brief ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH2 FALSE
-#endif
-
-/**
- * @brief ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH3 FALSE
-#endif
-
-/**
- * @brief ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH4 FALSE
-#endif
-
-/**
- * @brief ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH5 FALSE
-#endif
-
-/**
- * @brief ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH6 FALSE
-#endif
-
-/**
- * @brief ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH7 FALSE
-#endif
-
-/**
- * @brief ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH24 FALSE
-#endif
-
-/**
- * @brief ICUD1 and ICUD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD3 and ICUD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD5 and ICUD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD7 and ICUD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS1_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS1_CH24 FALSE
-#endif
-
-/**
- * @brief ICUD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_ICU_USE_EMIOS0 (SPC5_ICU_USE_EMIOS0_CH0 || \
- SPC5_ICU_USE_EMIOS0_CH1 || \
- SPC5_ICU_USE_EMIOS0_CH2 || \
- SPC5_ICU_USE_EMIOS0_CH3 || \
- SPC5_ICU_USE_EMIOS0_CH4 || \
- SPC5_ICU_USE_EMIOS0_CH5 || \
- SPC5_ICU_USE_EMIOS0_CH6 || \
- SPC5_ICU_USE_EMIOS0_CH7 || \
- SPC5_ICU_USE_EMIOS0_CH24)
-
-#define SPC5_ICU_USE_EMIOS1 SPC5_ICU_USE_EMIOS1_CH24
-
-#if !SPC5_ICU_USE_EMIOS0 && !SPC5_ICU_USE_EMIOS1
-#error "ICU driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
- ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
- ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
-} icumode_t;
-
-/**
- * @brief ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Driver mode.
- */
- icumode_t mode;
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- icufreq_t frequency;
- /**
- * @brief Callback for pulse width measurement.
- */
- icucallback_t width_cb;
- /**
- * @brief Callback for cycle period measurement.
- */
- icucallback_t period_cb;
- /**
- * @brief Callback for timer overflow.
- */
- icucallback_t overflow_cb;
- /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief Structure representing an ICU driver.
- */
-struct ICUDriver {
- /**
- * @brief Driver state.
- */
- icustate_t state;
- /**
- * @brief eMIOSx channel number.
- */
- uint32_t ch_number;
- /**
- * @brief Current configuration data.
- */
- const ICUConfig *config;
- /**
- * @brief CH Counter clock.
- */
- uint32_t clock;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
- /**
- * @brief CCR register used for width capture.
- */
- volatile vint16_t *wccrp;
- /**
- * @brief CCR register used for period capture.
- */
- volatile vint16_t *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- * edge and the stop edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- * edge and the next start edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_EMIOS1_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void icu_lld_init(void);
- void icu_lld_start(ICUDriver *icup);
- void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c deleted file mode 100644 index f353b180a..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c +++ /dev/null @@ -1,1759 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/pwm_lld.c
- * @brief SPC5xx low level PWM driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the unified channels eMIOS0_CH8 -
- * eMIOS0_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the unified channels eMIOS0_CH16 -
- * eMIOS0_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the unified channels eMIOS1_CH0 -
- * eMIOS1_CH7 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief PWMD4 driver identifier.
- * @note The driver PWMD4 allocates the unified channels eMIOS1_CH8 -
- * eMIOS1_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief PWMD5 driver identifier.
- * @note The driver PWMD5 allocates the unified channels eMIOS1_CH16 -
- * eMIOS1_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP2 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief PWM IRQ handler.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt1(PWMDriver *pwmp, uint32_t index) {
-
- uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
- if (sr & EMIOSS_OVFL) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
- }
- if (sr & EMIOSS_OVR) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
- }
- if (sr & EMIOSS_FLAG) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
- if (pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- }
- }
-
-}
-
-static void pwm_lld_serve_interrupt2(PWMDriver *pwmp, uint32_t index) {
-
- uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
- if (sr & EMIOSS_OVFL) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
- }
- if (sr & EMIOSS_OVR) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
- }
- if (sr & EMIOSS_FLAG) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
- if (pwmp->config->channels[index%8U - 1].callback != NULL) {
- pwmp->config->channels[index%8U - 1].callback(pwmp);
- }
- }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-#if !defined(SPC5_EMIOS0_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS0_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 8 and 9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F8F9_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 8U)) {
- pwm_lld_serve_interrupt1(&PWMD1, 8U);
- }
- if (gfr & (1U << 9U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 9U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS0_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 10 and 11 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F10F11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 10U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 10U);
- }
- if (gfr & (1U << 11U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 11U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS0_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 12 and 13 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F12F13_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 12U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 12U);
- }
- if (gfr & (1U << 13U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 13U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS0_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 14 and 15 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F14F15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr && (1U << 14U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 14U);
- }
- if (gfr && (1U << 15U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 15U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-#if !defined(SPC5_EMIOS0_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS0_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 16 and 17 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F16F17_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 16U)) {
- pwm_lld_serve_interrupt1(&PWMD2, 16U);
- }
- if (gfr && (1U << 17U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 17U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS0_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 18 and 19 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F18F19_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 18U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 18U);
- }
- if (gfr && (1U << 19U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 19U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS0_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 20 and 21 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F20F21_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 20U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 20U);
- }
- if (gfr && (1U << 21U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 21U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS0_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 22 and 23 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F22F23_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 22U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 22U);
- }
- if (gfr && (1U << 23U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 23U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-#if !defined(SPC5_EMIOS1_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS1_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 0 and 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F0F1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 0)) {
- pwm_lld_serve_interrupt1(&PWMD3, 0);
- }
- if (gfr && (1U << 1U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 1U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS1_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 2 and 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F2F3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 2U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 2U);
- }
- if (gfr && (1U << 3U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 3U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS1_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 4 and 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F4F5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 4U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 4U);
- }
- if (gfr && (1U << 5U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 5U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS1_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 6 and 7 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F6F7_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 6U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 6U);
- }
- if (gfr && (1U << 7U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 7U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-#if !defined(SPC5_EMIOS1_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS1_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 8 and 9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F8F9_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 8U)) {
- pwm_lld_serve_interrupt1(&PWMD4, 8U);
- }
- if (gfr && (1U << 9U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 9U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS1_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 10 and 11 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F10F11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 10U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 10U);
- }
- if (gfr && (1U << 11U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 11U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS1_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 12 and 13 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F12F13_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 12U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 12U);
- }
- if (gfr && (1U << 13U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 13U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS1_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 14 and 15 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F14F15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 14U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 14U);
- }
- if (gfr && (1U << 15U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 15U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-#if !defined(SPC5_EMIOS1_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS1_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 16 and 17 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F16F17_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 16U)) {
- pwm_lld_serve_interrupt1(&PWMD5, 16U);
- }
- if (gfr && (1U << 17U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 17U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS1_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 18 and 19 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F18F19_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 18U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 18U);
- }
- if (gfr && (1U << 19U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 19U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS1_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 20 and 21 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F20F21_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 20U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 20U);
- }
- if (gfr && (1U << 21U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 21U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS1_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 22 and 23 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 22U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 22U);
- }
- if (gfr && (1U << 23U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 23U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
- /* eMIOSx channels initially all not in use.*/
- reset_emios0_active_channels();
- reset_emios1_active_channels();
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- /* Driver initialization.*/
- pwmObjectInit(&PWMD1);
- PWMD1.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- /* Driver initialization.*/
- pwmObjectInit(&PWMD2);
- PWMD2.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- /* Driver initialization.*/
- pwmObjectInit(&PWMD3);
- PWMD3.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- /* Driver initialization.*/
- pwmObjectInit(&PWMD4);
- PWMD4.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- /* Driver initialization.*/
- pwmObjectInit(&PWMD5);
- PWMD5.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-#if SPC5_PWM_USE_EMIOS0
-
- INTC.PSR[SPC5_EMIOS0_GFR_F8F9_NUMBER].R = SPC5_EMIOS0_GFR_F8F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F10F11_NUMBER].R = SPC5_EMIOS0_GFR_F10F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F12F13_NUMBER].R = SPC5_EMIOS0_GFR_F12F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F14F15_NUMBER].R = SPC5_EMIOS0_GFR_F14F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F16F17_NUMBER].R = SPC5_EMIOS0_GFR_F16F17_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F18F19_NUMBER].R = SPC5_EMIOS0_GFR_F18F19_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F20F21_NUMBER].R = SPC5_EMIOS0_GFR_F20F21_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F22F23_NUMBER].R = SPC5_EMIOS0_GFR_F22F23_PRIORITY;
-
-#endif
-
-#if SPC5_PWM_USE_EMIOS1
-
- INTC.PSR[SPC5_EMIOS1_GFR_F0F1_NUMBER].R = SPC5_EMIOS1_GFR_F0F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F2F3_NUMBER].R = SPC5_EMIOS1_GFR_F2F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F4F5_NUMBER].R = SPC5_EMIOS1_GFR_F4F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F6F7_NUMBER].R = SPC5_EMIOS1_GFR_F6F7_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F8F9_NUMBER].R = SPC5_EMIOS1_GFR_F8F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F10F11_NUMBER].R = SPC5_EMIOS1_GFR_F10F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F12F13_NUMBER].R = SPC5_EMIOS1_GFR_F12F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F14F15_NUMBER].R = SPC5_EMIOS1_GFR_F14F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F16F17_NUMBER].R = SPC5_EMIOS1_GFR_F16F17_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F18F19_NUMBER].R = SPC5_EMIOS1_GFR_F18F19_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F20F21_NUMBER].R = SPC5_EMIOS1_GFR_F20F21_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F22F23_NUMBER].R = SPC5_EMIOS1_GFR_F22F23_PRIORITY;
-
-#endif
-
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
- uint32_t psc = 0, i = 0;
-
- chDbgAssert(get_emios0_active_channels() < 28,
- "pwm_lld_start(), #1", "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28,
- "pwm_lld_start(), #2", "too many channels");
-
- if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- increase_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- increase_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
- /* Set eMIOS0 Clock.*/
-#if SPC5_PWM_USE_EMIOS0
- active_emios0_clock(NULL, pwmp);
-#endif
-
- /* Set eMIOS1 Clock.*/
-#if SPC5_PWM_USE_EMIOS1
- active_emios1_clock(NULL, pwmp);
-#endif
-
- }
- /* Configures the peripheral.*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~1U;
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[0].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
- /* Set clock prescaler and control register.*/
- if (pwmp->emiosp == &EMIOS_0) {
- psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "pwm_lld_start(), #1", "invalid frequency");
- } else if (pwmp->emiosp == &EMIOS_1) {
- psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "pwm_lld_start(), #2", "invalid frequency");
- }
-
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
-
- pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[8U].CCNTR.R = 1U;
- pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 0;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
-
- pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[16U].CCNTR.R = 1U;
- pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 0;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
-
- pwmp->emiosp->CH[0].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[0].CCNTR.R = 1U;
- pwmp->emiosp->CH[0].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[0].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[0].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[0].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[0].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 1U].CADR.R = 0;
- pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 1U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 1U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= 1U;
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
-
- pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[8U].CCNTR.R = 1U;
- pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 0;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
-
- pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[16U].CCNTR.R = 1U;
- pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 0;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
- }
- }
-#endif
-
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- uint32_t i = 0;
-
- chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1",
- "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2",
- "too many channels");
-
- if (pwmp->state == PWM_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 8U].CCR.R = 0;
- }
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 16U].CCR.R = 0;
- }
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 8U].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 16U].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
- /* eMIOS0 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS0
- deactive_emios0_clock(NULL, pwmp);
-#endif
-
- /* eMIOS1 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS1
- deactive_emios1_clock(NULL, pwmp);
-#endif
- }
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[8U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[16U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[0].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[8U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[16U].CADR.R = period;
- }
-#endif
-
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 1U].CBDR.R = width;
-
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & 1U) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~1U;
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[0].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 17));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 1U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & 0xFE) == 0xFE) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[0].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= 1U;
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 17U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
- }
-
- }
-#endif
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h deleted file mode 100644 index e2dc403a8..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h +++ /dev/null @@ -1,420 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/pwm_lld.h
- * @brief SPC5xx low level PWM driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 7
-
-/**
- * @brief Edge-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE 0x00
-
-/**
- * @brief Center-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER 0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0__GROUP0 FALSE
-#endif
-
-/**
- * @brief PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE
-#endif
-
-/**
- * @brief PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE
-#endif
-
-/**
- * @brief PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_PWM_USE_EMIOS0 (SPC5_PWM_USE_EMIOS0_GROUP0 || \
- SPC5_PWM_USE_EMIOS0_GROUP1)
-
-#define SPC5_PWM_USE_EMIOS1 (SPC5_PWM_USE_EMIOS1_GROUP0 || \
- SPC5_PWM_USE_EMIOS1_GROUP1 || \
- SPC5_PWM_USE_EMIOS1_GROUP2)
-
-#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1
-#error "PWM driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief PWM counter type.
- */
-typedef uint32_t pwmcnt_t;
-
-/**
- * @brief PWM driver channel configuration structure.
- * @note Some architectures may not be able to support the channel mode
- * or the callback, in this case the fields are ignored.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
- /**
- * @brief PWM functional mode.
- */
- pwmmode_t mode;
-} PWMConfig;
-
-/**
- * @brief Structure representing an PWM driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c deleted file mode 100644 index 20ce38773..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c +++ /dev/null @@ -1,195 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/spc5_emios.c
- * @brief SPC5xx low level ICU and PWM drivers common code.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active eMIOSx Channels.
- */
-static uint32_t emios0_active_channels;
-static uint32_t emios1_active_channels;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-void reset_emios0_active_channels() {
- emios0_active_channels = 0;
-}
-
-void reset_emios1_active_channels() {
- emios1_active_channels = 0;
-}
-
-uint32_t get_emios0_active_channels() {
- return emios0_active_channels;
-}
-
-uint32_t get_emios1_active_channels() {
- return emios1_active_channels;
-}
-
-void increase_emios0_active_channels() {
- emios0_active_channels++;
-}
-
-void decrease_emios0_active_channels() {
- emios0_active_channels--;
-}
-
-void increase_emios1_active_channels() {
- emios1_active_channels++;
-}
-
-void decrease_emios1_active_channels() {
- emios1_active_channels--;
-}
-
-void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If this is the first Channel activated then the eMIOS0 is enabled.*/
- if (emios0_active_channels == 1) {
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_START_PCTL);
-
- /* Disable all unified channels.*/
- if (icup != NULL) {
- icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
-
- icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- } else if (pwmp != NULL) {
- pwmp->emiosp->MCR.B.GPREN = 0;
- pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- pwmp->emiosp->MCR.B.GTBE = 1U;
-
- pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- }
-
- }
-}
-
-void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If this is the first Channel activated then the eMIOS1 is enabled.*/
- if (emios1_active_channels == 1) {
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_START_PCTL);
-
- /* Disable all unified channels.*/
- if (icup != NULL) {
- icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
-
- icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- } else if (pwmp != NULL) {
- pwmp->emiosp->MCR.B.GPREN = 0;
- pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- pwmp->emiosp->MCR.B.GTBE = 1U;
-
- pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- }
-
- }
-}
-
-void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If it is the last active channels then the eMIOS0 is disabled.*/
- if (emios0_active_channels == 0) {
- if (icup != NULL) {
- if (icup->emiosp->UCDIS.R == 0) {
- //icup->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_STOP_PCTL);
- }
- } else if (pwmp != NULL) {
- if (pwmp->emiosp->UCDIS.R == 0) {
- //pwmp->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_STOP_PCTL);
- }
- }
- }
-}
-
-void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If it is the last active channels then the eMIOS1 is disabled.*/
- if (emios1_active_channels == 0) {
- if (icup != NULL) {
- if (icup->emiosp->UCDIS.R == 0) {
- //icup->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_STOP_PCTL);
- }
- } else if (pwmp != NULL) {
- if (pwmp->emiosp->UCDIS.R == 0) {
- //pwmp->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_STOP_PCTL);
- }
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h deleted file mode 100644 index 946db2400..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h +++ /dev/null @@ -1,169 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/spc5_emios.h
- * @brief SPC5xx low level ICU - PWM driver common header.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#ifndef _SPC5_EMIOS_H_
-#define _SPC5_EMIOS_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define EMIOSMCR_MDIS (1U << 30U)
-#define EMIOSMCR_FRZ (1U << 29U)
-#define EMIOSMCR_GTBE (1U << 28U)
-#define EMIOSMCR_GPREN (1U << 26U)
-#define EMIOSMCR_GPRE(n) ((n) << 8U)
-
-#define EMIOSC_FREN (1U << 31U)
-#define EMIOSC_UCPRE(n) ((n) << 26U)
-#define EMIOSC_UCPREN (1U << 25U)
-#define EMIOSC_DMA (1U << 24U)
-#define EMIOSC_IF(n) ((n) << 19U)
-#define EMIOSC_FCK (1U << 18U)
-#define EMIOSC_FEN (1U << 17U)
-#define EMIOSC_FORCMA (1U << 13U)
-#define EMIOSC_FORCMB (1U << 12U)
-#define EMIOSC_BSL(n) ((n) << 9U)
-#define EMIOSC_EDSEL (1U << 8U)
-#define EMIOSC_EDPOL (1U << 7U)
-#define EMIOSC_MODE(n) ((n) << 0)
-
-#define EMIOS_BSL_COUNTER_BUS_A 0
-#define EMIOS_BSL_COUNTER_BUS_2 1U
-#define EMIOS_BSL_INTERNAL_COUNTER 3U
-
-#define EMIOS_CCR_MODE_GPIO_IN 0
-#define EMIOS_CCR_MODE_GPIO_OUT 1U
-#define EMIOS_CCR_MODE_SAIC 2U
-#define EMIOS_CCR_MODE_SAOC 3U
-#define EMIOS_CCR_MODE_IPWM 4U
-#define EMIOS_CCR_MODE_IPM 5U
-#define EMIOS_CCR_MODE_DAOC_B_MATCH 6U
-#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7U
-#define EMIOS_CCR_MODE_MC_CMS 16U
-#define EMIOS_CCR_MODE_MC_CME 17U
-#define EMIOS_CCR_MODE_MC_UP_DOWN 18U
-#define EMIOS_CCR_MODE_OPWMT 38U
-#define EMIOS_CCR_MODE_MCB_UP 80U
-#define EMIOS_CCR_MODE_MCB_UP_DOWN 84U
-#define EMIOS_CCR_MODE_OPWFMB 88U
-#define EMIOS_CCR_MODE_OPWMCB_TE 92U
-#define EMIOS_CCR_MODE_OPWMCB_LE 93U
-#define EMIOS_CCR_MODE_OPWMB 96U
-
-#define EMIOSS_OVR (1U << 31U)
-#define EMIOSS_OVRC (1U << 31U)
-#define EMIOSS_OVFL (1U << 15U)
-#define EMIOSS_OVFLC (1U << 15U)
-#define EMIOSS_FLAG (1U << 0)
-#define EMIOSS_FLAGC (1U << 0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-#if SPC5_HAS_EMIOS0
-/**
- * @brief eMIOS0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eMIOS0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1
-/**
- * @brief eMIOS1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eMIOS1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-void reset_emios0_active_channels(void);
-void reset_emios1_active_channels(void);
-uint32_t get_emios0_active_channels(void);
-uint32_t get_emios1_active_channels(void);
-void increase_emios0_active_channels(void);
-void decrease_emios0_active_channels(void);
-void increase_emios1_active_channels(void);
-void decrease_emios1_active_channels(void);
-void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _SPC5_EMIOS_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c deleted file mode 100644 index 4cdfab8f7..000000000 --- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c +++ /dev/null @@ -1,1389 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eTimer_v1/icu_lld.c
- * @brief SPC5xx low level ICU driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief ICUD1 driver identifier.
- * @note The driver ICUD1 allocates the complex timer SMOD0 when enabled.
- */
-#if SPC5_ICU_USE_SMOD0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief ICUD2 driver identifier.
- * @note The driver ICUD2 allocates the complex timer SMOD1 when enabled.
- */
-#if SPC5_ICU_USE_SMOD1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief ICUD3 driver identifier.
- * @note The driver ICUD3 allocates the complex timer SMOD2 when enabled.
- */
-#if SPC5_ICU_USE_SMOD2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief ICUD4 driver identifier.
- * @note The driver ICUD4 allocates the complex timer SMOD3 when enabled.
- */
-#if SPC5_ICU_USE_SMOD3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief ICUD5 driver identifier.
- * @note The driver ICUD5 allocates the complex timer SMOD4 when enabled.
- */
-#if SPC5_ICU_USE_SMOD4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief ICUD6 driver identifier.
- * @note The driver ICUD6 allocates the complex timer SMOD5 when enabled.
- */
-#if SPC5_ICU_USE_SMOD5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief ICUD7 driver identifier.
- * @note The driver ICUD7 allocates the complex timer SMOD6 when enabled.
- */
-#if SPC5_ICU_USE_SMOD6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief ICUD8 driver identifier.
- * @note The driver ICUD8 allocates the complex timer SMOD7 when enabled.
- */
-#if SPC5_ICU_USE_SMOD7 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief ICUD9 driver identifier.
- * @note The driver ICUD9 allocates the complex timer SMOD8 when enabled.
- */
-#if SPC5_ICU_USE_SMOD8 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief ICUD10 driver identifier.
- * @note The driver ICUD10 allocates the complex timer SMOD9 when enabled.
- */
-#if SPC5_ICU_USE_SMOD9 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/**
- * @brief ICUD11 driver identifier.
- * @note The driver ICUD11 allocates the complex timer SMOD10 when enabled.
- */
-#if SPC5_ICU_USE_SMOD10 || defined(__DOXYGEN__)
-ICUDriver ICUD11;
-#endif
-
-/**
- * @brief ICUD12 driver identifier.
- * @note The driver ICUD12 allocates the complex timer SMOD11 when enabled.
- */
-#if SPC5_ICU_USE_SMOD11 || defined(__DOXYGEN__)
-ICUDriver ICUD12;
-#endif
-
-/**
- * @brief ICUD13 driver identifier.
- * @note The driver ICUD13 allocates the complex timer SMOD12 when enabled.
- */
-#if SPC5_ICU_USE_SMOD12 || defined(__DOXYGEN__)
-ICUDriver ICUD13;
-#endif
-
-/**
- * @brief ICUD14 driver identifier.
- * @note The driver ICUD14 allocates the complex timer SMOD13 when enabled.
- */
-#if SPC5_ICU_USE_SMOD13 || defined(__DOXYGEN__)
-ICUDriver ICUD14;
-#endif
-
-/**
- * @brief ICUD15 driver identifier.
- * @note The driver ICUD15 allocates the complex timer SMOD14 when enabled.
- */
-#if SPC5_ICU_USE_SMOD14 || defined(__DOXYGEN__)
-ICUDriver ICUD15;
-#endif
-
-/**
- * @brief ICUD16 driver identifier.
- * @note The driver ICUD16 allocates the complex timer SMOD15 when enabled.
- */
-#if SPC5_ICU_USE_SMOD15 || defined(__DOXYGEN__)
-ICUDriver ICUD16;
-#endif
-
-/**
- * @brief ICUD17 driver identifier.
- * @note The driver ICUD17 allocates the complex timer SMOD16 when enabled.
- */
-#if SPC5_ICU_USE_SMOD16 || defined(__DOXYGEN__)
-ICUDriver ICUD17;
-#endif
-
-/**
- * @brief ICUD18 driver identifier.
- * @note The driver ICUD18 allocates the complex timer SMOD17 when enabled.
- */
-#if SPC5_ICU_USE_SMOD17 || defined(__DOXYGEN__)
-ICUDriver ICUD18;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active eTimer Submodules.
- */
-static uint32_t icu_active_submodules0;
-static uint32_t icu_active_submodules1;
-static uint32_t icu_active_submodules2;
-
-/**
- * @brief Width and Period registers.
- */
-uint16_t width;
-uint16_t period;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Shared IRQ handler.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
- uint16_t sr = icup->etimerp->CHANNEL[icup->smod_number].STS.R &
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R;
-
- if (ICU_SKIP_FIRST_CAPTURE) {
- if ((sr & 0x0008) != 0) { /* TOF */
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U;
- _icu_isr_invoke_overflow_cb(icup);
- }
- if ((sr & 0x0040) != 0) { /* ICF1 */
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
- SPC5_ETIMER_CNTMODE_RFE_SIHA) {
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
- SPC5_ETIMER_CNTMODE_RE;
- }
- else {
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- } else {
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- }
- _icu_isr_invoke_period_cb(icup);
- }
- }
- else if ((sr & 0x0080) != 0) { /* ICF2 */
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
- SPC5_ETIMER_CNTMODE_RFE_SIHA) {
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
- icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0;
- }
- else {
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- } else {
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- }
- _icu_isr_invoke_width_cb(icup);
- }
- }
- } else { /* ICU_SKIP_FIRST_CAPTURE = TRUE*/
- if ((sr & 0x0008) != 0) { /* TOF */
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U;
- _icu_isr_invoke_overflow_cb(icup);
- }
- if ((sr & 0x0040) != 0) { /* ICF1 */
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- } else {
- period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
- }
- _icu_isr_invoke_period_cb(icup);
- }
- else if ((sr & 0x0080) != 0) { /* ICF2 */
- icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
- if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- } else {
- width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
- }
- _icu_isr_invoke_width_cb(icup);
- }
- } /* ICU_SKIP_FIRST_CAPTURE = FALSE */
-}
-
-/**
- * @brief eTimer SubModules initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp pointer to a @p ICUDriver object
- * @param[in] config the architecture-dependent ICU driver configuration
- */
-static void spc5_icu_smod_init(ICUDriver *icup) {
- uint32_t psc = (icup->clock / icup->config->frequency);
-
- chDbgAssert((psc <= 0xFFFF) &&
- ((psc * icup->config->frequency) == icup->clock) &&
- ((psc == 1) || (psc == 2) || (psc == 4) ||
- (psc == 8) || (psc == 16) || (psc == 32) ||
- (psc == 64) || (psc == 128)),
- "spc5_icu_smod_init(), #1", "invalid frequency");
-
- /* Set primary source and clock prescaler.*/
- switch (psc) {
- case 1:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1;
- break;
- case 2:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2;
- break;
- case 4:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4;
- break;
- case 8:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8;
- break;
- case 16:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16;
- break;
- case 32:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32;
- break;
- case 64:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64;
- break;
- case 128:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
- SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128;
- break;
- }
-
- /* Set control registers.*/
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.ONCE = 0U;
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.LENGTH = 0U;
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.DIR = 0U;
- icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U;
-
- /* Set secondary source.*/
- switch (icup->smod_number) {
- case 0:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_0_INPUT_PIN;
- break;
- case 1:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_1_INPUT_PIN;
- break;
- case 2:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_2_INPUT_PIN;
- break;
- case 3:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_3_INPUT_PIN;
- break;
- case 4:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_4_INPUT_PIN;
- break;
- case 5:
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
- SPC5_ETIMER_COUNTER_5_INPUT_PIN;
- break;
- }
-
- /* Set secondary source polarity.*/
- if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
- icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 0U;
- }
- else {
- icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 1U;
- }
-
- /* Direct pointers to the capture registers in order to make reading
- data faster from within callbacks.*/
- icup->pccrp = .
- icup->wccrp = &width;
-
- /* Enable channel.*/
- icup->etimerp->ENBL.B.ENBL |= 1U << (icup->smod_number);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_SMOD0
-#if !defined(SPC5_ETIMER0_TC0IR_HANDLER)
-#error "SPC5_ETIMER0_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 0 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC0IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD1);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD0 */
-
-#if SPC5_ICU_USE_SMOD1
-#if !defined(SPC5_ETIMER0_TC1IR_HANDLER)
-#error "SPC5_ETIMER0_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC1IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD1 */
-
-#if SPC5_ICU_USE_SMOD2
-#if !defined(SPC5_ETIMER0_TC2IR_HANDLER)
-#error "SPC5_ETIMER0_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 2 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC2IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD3);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD2 */
-
-#if SPC5_ICU_USE_SMOD3
-#if !defined(SPC5_ETIMER0_TC3IR_HANDLER)
-#error "SPC5_ETIMER0_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC3IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD4);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD3 */
-
-#if SPC5_ICU_USE_SMOD4
-#if !defined(SPC5_ETIMER0_TC4IR_HANDLER)
-#error "SPC5_ETIMER0_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 4 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC4IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD4 */
-
-#if SPC5_ICU_USE_SMOD5
-#if !defined(SPC5_ETIMER0_TC5IR_HANDLER)
-#error "SPC5_ETIMER0_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer0 Channel 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC5IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD6);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD5 */
-
-#if SPC5_ICU_USE_SMOD6
-#if !defined(SPC5_ETIMER1_TC0IR_HANDLER)
-#error "SPC5_ETIMER1_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 0 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC0IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD7);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD6 */
-
-#if SPC5_ICU_USE_SMOD7
-#if !defined(SPC5_ETIMER1_TC1IR_HANDLER)
-#error "SPC5_ETIMER1_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC1IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD8);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD7 */
-
-#if SPC5_ICU_USE_SMOD8
-#if !defined(SPC5_ETIMER1_TC2IR_HANDLER)
-#error "SPC5_ETIMER1_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 2 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC2IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD9);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD8 */
-
-#if SPC5_ICU_USE_SMOD9
-#if !defined(SPC5_ETIMER1_TC3IR_HANDLER)
-#error "SPC5_ETIMER1_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC3IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD10);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD9 */
-
-#if SPC5_ICU_USE_SMOD10
-#if !defined(SPC5_ETIMER1_TC4IR_HANDLER)
-#error "SPC5_ETIMER1_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 4 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC4IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD11);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD10 */
-
-#if SPC5_ICU_USE_SMOD11
-#if !defined(SPC5_ETIMER1_TC5IR_HANDLER)
-#error "SPC5_ETIMER1_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer1 Channel 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC5IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD12);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD11 */
-
-#if SPC5_ICU_USE_SMOD12
-#if !defined(SPC5_ETIMER2_TC0IR_HANDLER)
-#error "SPC5_ETIMER2_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 0 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC0IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD13);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD12 */
-
-#if SPC5_ICU_USE_SMOD13
-#if !defined(SPC5_ETIMER2_TC1IR_HANDLER)
-#error "SPC5_ETIMER2_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC1IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD14);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD13 */
-
-#if SPC5_ICU_USE_SMOD14
-#if !defined(SPC5_ETIMER2_TC2IR_HANDLER)
-#error "SPC5_ETIMER2_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 2 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC2IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD15);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD14 */
-
-#if SPC5_ICU_USE_SMOD15
-#if !defined(SPC5_ETIMER2_TC3IR_HANDLER)
-#error "SPC5_ETIMER2_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC3IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD16);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD15 */
-
-#if SPC5_ICU_USE_SMOD16
-#if !defined(SPC5_ETIMER2_TC4IR_HANDLER)
-#error "SPC5_ETIMER2_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 4 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC4IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD17);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD16 */
-
-#if SPC5_ICU_USE_SMOD17
-#if !defined(SPC5_ETIMER2_TC5IR_HANDLER)
-#error "SPC5_ETIMER2_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief eTimer2 Channel 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC5IR_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- icu_lld_serve_interrupt(&ICUD18);
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD17 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
- /* Submodules initially all not in use.*/
- icu_active_submodules0 = 0;
- icu_active_submodules1 = 0;
- icu_active_submodules2 = 0;
-
- /* Reset width and period registers.*/
- width = 0;
- period = 0;
-
-#if SPC5_ICU_USE_SMOD0
- /* Driver initialization.*/
- icuObjectInit(&ICUD1);
- ICUD1.etimerp = &SPC5_ETIMER_0;
- ICUD1.smod_number = 0U;
- ICUD1.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD1
- /* Driver initialization.*/
- icuObjectInit(&ICUD2);
- ICUD2.etimerp = &SPC5_ETIMER_0;
- ICUD2.smod_number = 1U;
- ICUD2.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD2
- /* Driver initialization.*/
- icuObjectInit(&ICUD3);
- ICUD3.etimerp = &SPC5_ETIMER_0;
- ICUD3.smod_number = 2U;
- ICUD3.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD3
- /* Driver initialization.*/
- icuObjectInit(&ICUD4);
- ICUD4.etimerp = &SPC5_ETIMER_0;
- ICUD4.smod_number = 3U;
- ICUD4.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD4
- /* Driver initialization.*/
- icuObjectInit(&ICUD5);
- ICUD5.etimerp = &SPC5_ETIMER_0;
- ICUD5.smod_number = 4U;
- ICUD5.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD5
- /* Driver initialization.*/
- icuObjectInit(&ICUD6);
- ICUD6.etimerp = &SPC5_ETIMER_0;
- ICUD6.smod_number = 5U;
- ICUD6.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD6
- /* Driver initialization.*/
- icuObjectInit(&ICUD7);
- ICUD7.etimerp = &SPC5_ETIMER_1;
- ICUD7.smod_number = 0U;
- ICUD7.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD7
- /* Driver initialization.*/
- icuObjectInit(&ICUD8);
- ICUD8.etimerp = &SPC5_ETIMER_1;
- ICUD8.smod_number = 1U;
- ICUD8.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD8
- /* Driver initialization.*/
- icuObjectInit(&ICUD9);
- ICUD9.etimerp = &SPC5_ETIMER_1;
- ICUD9.smod_number = 2U;
- ICUD9.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD9
- /* Driver initialization.*/
- icuObjectInit(&ICUD10);
- ICUD10.etimerp = &SPC5_ETIMER_1;
- ICUD10.smod_number = 3U;
- ICUD10.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD10
- /* Driver initialization.*/
- icuObjectInit(&ICUD11);
- ICUD11.etimerp = &SPC5_ETIMER_1;
- ICUD11.smod_number = 4U;
- ICUD11.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD11
- /* Driver initialization.*/
- icuObjectInit(&ICUD12);
- ICUD12.etimerp = &SPC5_ETIMER_1;
- ICUD12.smod_number = 5U;
- ICUD12.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD12
- /* Driver initialization.*/
- icuObjectInit(&ICUD13);
- ICUD13.etimerp = &SPC5_ETIMER_2;
- ICUD13.smod_number = 0U;
- ICUD13.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD13
- /* Driver initialization.*/
- icuObjectInit(&ICUD14);
- ICUD14.etimerp = &SPC5_ETIMER_2;
- ICUD14.smod_number = 1U;
- ICUD14.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD14
- /* Driver initialization.*/
- icuObjectInit(&ICUD15);
- ICUD15.etimerp = &SPC5_ETIMER_2;
- ICUD15.smod_number = 2U;
- ICUD15.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD15
- /* Driver initialization.*/
- icuObjectInit(&ICUD16);
- ICUD16.etimerp = &SPC5_ETIMER_2;
- ICUD16.smod_number = 3U;
- ICUD16.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD16
- /* Driver initialization.*/
- icuObjectInit(&ICUD17);
- ICUD17.etimerp = &SPC5_ETIMER_2;
- ICUD17.smod_number = 4U;
- ICUD17.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD17
- /* Driver initialization.*/
- icuObjectInit(&ICUD18);
- ICUD18.etimerp = &SPC5_ETIMER_2;
- ICUD18.smod_number = 5U;
- ICUD18.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_ETIMER0
-
- INTC.PSR[SPC5_ETIMER0_TC0IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_TC1IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_TC2IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_TC3IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_TC4IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_TC5IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_WTIF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
- INTC.PSR[SPC5_ETIMER0_RCF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_ETIMER1
-
- INTC.PSR[SPC5_ETIMER1_TC0IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_TC1IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_TC2IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_TC3IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_TC4IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_TC5IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
- INTC.PSR[SPC5_ETIMER1_RCF_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_ETIMER2
-
- INTC.PSR[SPC5_ETIMER2_TC0IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_TC1IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_TC2IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_TC3IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_TC4IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_TC5IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
- INTC.PSR[SPC5_ETIMER2_RCF_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-
-#endif
-}
-
-/**
- * @brief Configures and activates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
- chDbgAssert(icu_active_submodules0 < 6, "icu_lld_start(), #1",
- "too many submodules");
- chDbgAssert(icu_active_submodules1 < 6, "icu_lld_start(), #2",
- "too many submodules");
- chDbgAssert(icu_active_submodules2 < 6, "icu_lld_start(), #3",
- "too many submodules");
-
- if (icup->state == ICU_STOP) {
-#if SPC5_ICU_USE_SMOD0
- if (&ICUD1 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD1
- if (&ICUD2 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD2
- if (&ICUD3 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD3
- if (&ICUD4 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD4
- if (&ICUD5 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD5
- if (&ICUD6 == icup)
- icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD6
- if (&ICUD7 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD7
- if (&ICUD8 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD8
- if (&ICUD9 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD9
- if (&ICUD10 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD10
- if (&ICUD11 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD11
- if (&ICUD12 == icup)
- icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD12
- if (&ICUD13 == icup)
- icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD13
- if (&ICUD14 == icup)
- icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD14
- if (&ICUD15 == icup)
- icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD15
- if (&ICUD16 == icup)
- icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD16
- if (&ICUD17 == icup)
- icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD17
- if (&ICUD18 == icup)
- icu_active_submodules2++;
-#endif
-
- /* Set eTimer0 Clock.*/
-#if SPC5_ICU_USE_ETIMER0
-
- /* If this is the first Submodule activated then the eTimer0 is enabled.*/
- if (icu_active_submodules0 == 1) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
- SPC5_ICU_ETIMER0_START_PCTL);
- }
-#endif
-
- /* Set eTimer1 Clock.*/
-#if SPC5_ICU_USE_ETIMER1
- /* If this is the first Submodule activated then the eTimer1 is enabled.*/
- if (icu_active_submodules1 == 1) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
- SPC5_ICU_ETIMER1_START_PCTL);
- }
-#endif
-
- /* Set eTimer2 Clock.*/
-#if SPC5_ICU_USE_ETIMER2
- /* If this is the first Submodule activated then the eTimer2 is enabled.*/
- if (icu_active_submodules2 == 1) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
- SPC5_ICU_ETIMER2_START_PCTL);
- }
-#endif
-
- /* Timer disabled.*/
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
- SPC5_ETIMER_CNTMODE_NO_OPERATION;
-
- /* Clear pending IRQs (if any).*/
- icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
- /* All IRQs and DMA requests disabled.*/
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0U;
-
- /* Compare Load 1 and Compare Load 2 disabled.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0U;
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0U;
-
- /* Capture 1 and Capture 2 disabled.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
- SPC5_ETIMER_CPT1MODE_DISABLED;
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
- SPC5_ETIMER_CPT2MODE_DISABLED;
-
- /* Counter reset to zero.*/
- icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0U;
- }
-
- /* Configuration.*/
- spc5_icu_smod_init(icup);
-}
-
-/**
- * @brief Deactivates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
- chDbgAssert(icu_active_submodules0 < 6, "icu_lld_stop(), #1",
- "too many submodules");
- chDbgAssert(icu_active_submodules1 < 6, "icu_lld_stop(), #2",
- "too many submodules");
- chDbgAssert(icu_active_submodules2 < 6, "icu_lld_stop(), #3",
- "too many submodules");
-
- if (icup->state == ICU_READY) {
-
-#if SPC5_ICU_USE_SMOD0
- if (&ICUD1 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFE;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD1
- if (&ICUD2 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFD;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD2
- if (&ICUD3 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFB;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD3
- if (&ICUD4 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xF7;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD4
- if (&ICUD5 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xEF;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD5
- if (&ICUD6 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xDF;
- icu_active_submodules0--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD6
- if (&ICUD7 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFE;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD7
- if (&ICUD8 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFD;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD8
- if (&ICUD9 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFB;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD9
- if (&ICUD10 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xF7;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD10
- if (&ICUD11 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xEF;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD11
- if (&ICUD12 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xDF;
- icu_active_submodules1--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD12
- if (&ICUD13 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFE;
- icu_active_submodules2--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD13
- if (&ICUD14 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFD;
- icu_active_submodules2--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD14
- if (&ICUD15 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xFB;
- icu_active_submodules2--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD15
- if (&ICUD16 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xF7;
- icu_active_submodules2--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD16
- if (&ICUD17 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xEF;
- icu_active_submodules2--;
- }
-#endif
-#if SPC5_ICU_USE_SMOD17
- if (&ICUD18 == icup) {
- /* Disable channel.*/
- icup->etimerp->ENBL.B.ENBL &= 0xDF;
- icu_active_submodules2--;
- }
-#endif
- /* eTimer0 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER0
- /* If it is the last active submodules then the eTimer0 is disabled.*/
- if (icu_active_submodules0 == 0) {
- if (icup->etimerp->ENBL.B.ENBL == 0) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
- SPC5_ICU_ETIMER0_STOP_PCTL);
- }
- }
-#endif
-
- /* eTimer1 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER1
- /* If it is the last active submodules then the eTimer1 is disabled.*/
- if (icu_active_submodules1 == 0) {
- if (icup->etimerp->ENBL.B.ENBL == 0) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
- SPC5_ICU_ETIMER1_STOP_PCTL);
- }
- }
-#endif
-
- /* eTimer2 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER2
- /* If it is the last active submodules then the eTimer2 is disabled.*/
- if (icu_active_submodules2 == 0) {
- if (icup->etimerp->ENBL.B.ENBL == 0) {
- halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
- SPC5_ICU_ETIMER2_STOP_PCTL);
- }
- }
-#endif
- }
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
- /* Clear pending IRQs (if any).*/
- icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
- /* Set Capture 1 and Capture 2 Mode.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
- SPC5_ETIMER_CPT1MODE_RISING_EDGE;
- icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.ROC =
- SPC5_ETIMER_ROC_REL_ON_CAP1;
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
- SPC5_ETIMER_CPT2MODE_FALLING_EDGE;
-
- /* Active interrupts.*/
- if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 1U;
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 1U;
- }
- if (icup->config->overflow_cb != NULL) {
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 1U;
- }
-
- /* Set Capture FIFO Water Mark.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CFWM = 0U;
-
- /* Enable Counter.*/
- if (ICU_SKIP_FIRST_CAPTURE) {
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
- SPC5_ETIMER_CNTMODE_RFE_SIHA;
- }
- else {
- icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
- SPC5_ETIMER_CNTMODE_RE;
- }
-
- /* Enable Capture process.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 1U;
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
- /* Disable Capture process.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 0U;
-
- /* Clear pending IRQs (if any).*/
- icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
- /* Set Capture 1 and Capture 2 Mode to Disabled.*/
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
- SPC5_ETIMER_CPT1MODE_DISABLED;
- icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
- SPC5_ETIMER_CPT2MODE_DISABLED;
-
- /* Disable interrupts.*/
- if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 0U;
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 0U;
- }
- if (icup->config->overflow_cb != NULL)
- icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 0U;
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h deleted file mode 100644 index f95f5356f..000000000 --- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h +++ /dev/null @@ -1,612 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eTimer_v1/icu_lld.h
- * @brief SPC5xx low level ICU driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_etimer.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Mode options
- * @{
- */
-
-/**
- * @brief Skip first capture cycle.
- * @details If set to @p TRUE the first capture cycle is skipped.
- * @note The default is @p FALSE.
- */
-#if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__)
-#define ICU_SKIP_FIRST_CAPTURE FALSE
-#endif
- -#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1 0x18
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2 0x19
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4 0x1A
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8 0x1B
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16 0x1C
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32 0x1D
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64 0x1E
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128 0x1F
-
-#define SPC5_ETIMER_COUNTER_0_INPUT_PIN 0U
-#define SPC5_ETIMER_COUNTER_1_INPUT_PIN 1U
-#define SPC5_ETIMER_COUNTER_2_INPUT_PIN 2U
-#define SPC5_ETIMER_COUNTER_3_INPUT_PIN 3U
-#define SPC5_ETIMER_COUNTER_4_INPUT_PIN 4U
-#define SPC5_ETIMER_COUNTER_5_INPUT_PIN 5U
-
-#define SPC5_ETIMER_CNTMODE_NO_OPERATION 0U
-#define SPC5_ETIMER_CNTMODE_RE 1U
-#define SPC5_ETIMER_CNTMODE_RFE 2U
-#define SPC5_ETIMER_CNTMODE_RFE_SIHA 3U
-#define SPC5_ETIMER_CNTMODE_QUADRATURE 4U
-#define SPC5_ETIMER_CNTMODE_RE_SSSD 5U
-#define SPC5_ETIMER_CNTMODE_ESS_TRIGGER 6U
-#define SPC5_ETIMER_CNTMODE_CASCADE 7U
-
-#define SPC5_ETIMER_CPT1MODE_DISABLED 0U
-#define SPC5_ETIMER_CPT1MODE_FALLING_EDGE 1U
-#define SPC5_ETIMER_CPT1MODE_RISING_EDGE 2U
-#define SPC5_ETIMER_CPT1MODE_ANY_EDGE 3U
-
-#define SPC5_ETIMER_CPT2MODE_DISABLED 0U
-#define SPC5_ETIMER_CPT2MODE_FALLING_EDGE 1U
-#define SPC5_ETIMER_CPT2MODE_RISING_EDGE 2U
-#define SPC5_ETIMER_CPT2MODE_ANY_EDGE 3U
-
-#define SPC5_ETIMER_ROC_DO_NOT_RELOAD 0U
-#define SPC5_ETIMER_ROC_REL_ON_CAP1 1U
-#define SPC5_ETIMER_ROC_REL_ON_CAP2 2U
-#define SPC5_ETIMER_ROC_REL_ON_CAP1_CAP2 3U
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD0 FALSE
-#endif
-
-/**
- * @brief ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD1 FALSE
-#endif
-
-/**
- * @brief ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD2 FALSE
-#endif
-
-/**
- * @brief ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD3 FALSE
-#endif
-
-/**
- * @brief ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD4 FALSE
-#endif
-
-/**
- * @brief ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD5 FALSE
-#endif
-
-/**
- * @brief eTimer0 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_PRIORITY 7
-#endif
-
-/**
- * @brief eTIMER0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eTIMER0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD6 FALSE
-#endif
-
-/**
- * @brief ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD7 FALSE
-#endif
-
-/**
- * @brief ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD8) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD8 FALSE
-#endif
-
-/**
- * @brief ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD9) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD9 FALSE
-#endif
-
-/**
- * @brief ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD10) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD10 FALSE
-#endif
-
-/**
- * @brief ICUD11 driver enable switch.
- * @details If set to @p TRUE the support for ICUD11 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD11) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD11 FALSE
-#endif
-
-/**
- * @brief eTimer1 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_PRIORITY 7
-#endif
-
-/**
- * @brief eTIMER1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eTIMER1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief ICUD13 driver enable switch.
- * @details If set to @p TRUE the support for ICUD13 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD12) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD12 FALSE
-#endif
-
-/**
- * @brief ICUD14 driver enable switch.
- * @details If set to @p TRUE the support for ICUD14 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD13) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD13 FALSE
-#endif
-
-/**
- * @brief ICUD15 driver enable switch.
- * @details If set to @p TRUE the support for ICUD15 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD14) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD14 FALSE
-#endif
-
-/**
- * @brief ICUD16 driver enable switch.
- * @details If set to @p TRUE the support for ICUD16 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD15) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD15 FALSE
-#endif
-
-/**
- * @brief ICUD17 driver enable switch.
- * @details If set to @p TRUE the support for ICUD17 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD16) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD16 FALSE
-#endif
-
-/**
- * @brief ICUD18 driver enable switch.
- * @details If set to @p TRUE the support for ICUD18 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD17) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD17 FALSE
-#endif
-
-/**
- * @brief eTimer2 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_PRIORITY 7
-#endif
-
-/**
- * @brief eTIMER2 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eTIMER2 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#define SPC5_ICU_USE_ETIMER0 (SPC5_ICU_USE_SMOD0 || \
- SPC5_ICU_USE_SMOD1 || \
- SPC5_ICU_USE_SMOD2 || \
- SPC5_ICU_USE_SMOD3 || \
- SPC5_ICU_USE_SMOD4 || \
- SPC5_ICU_USE_SMOD5)
-
-#define SPC5_ICU_USE_ETIMER1 (SPC5_ICU_USE_SMOD6 || \
- SPC5_ICU_USE_SMOD7 || \
- SPC5_ICU_USE_SMOD8 || \
- SPC5_ICU_USE_SMOD9 || \
- SPC5_ICU_USE_SMOD10 || \
- SPC5_ICU_USE_SMOD11)
-
-#define SPC5_ICU_USE_ETIMER2 (SPC5_ICU_USE_SMOD12 || \
- SPC5_ICU_USE_SMOD13 || \
- SPC5_ICU_USE_SMOD14 || \
- SPC5_ICU_USE_SMOD15 || \
- SPC5_ICU_USE_SMOD16 || \
- SPC5_ICU_USE_SMOD17)
-
-#if !SPC5_HAS_ETIMER0 && SPC5_ICU_USE_ETIMER0
-#error "ETIMER0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_ETIMER1 && SPC5_ICU_USE_ETIMER1
-#error "ETIMER1 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_ETIMER2 && SPC5_ICU_USE_ETIMER2
-#error "ETIMER2 not present in the selected device"
-#endif
-
-#if !SPC5_ICU_USE_ETIMER0 && !SPC5_ICU_USE_ETIMER1 && !SPC5_ICU_USE_ETIMER2
-#error "ICU driver activated but no SMOD peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
- ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
- ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
-} icumode_t;
-
-/**
- * @brief ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief ICU channel.
- */
-typedef enum {
- ICU_CHANNEL_1 = 0, /**< Use SMODxCH1. */
- ICU_CHANNEL_2 = 1, /**< Use SMODxCH2. */
- ICU_CHANNEL_3 = 2, /**< Use SMODxCH3. */
- ICU_CHANNEL_4 = 3, /**< Use SMODxCH4. */
- ICU_CHANNEL_5 = 4, /**< Use SMODxCH5. */
- ICU_CHANNEL_6 = 5, /**< Use SMODxCH6. */
-} icuchannel_t;
-
-/**
- * @brief ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Driver mode.
- */
- icumode_t mode;
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- icufreq_t frequency;
- /**
- * @brief Callback for pulse width measurement.
- */
- icucallback_t width_cb;
- /**
- * @brief Callback for cycle period measurement.
- */
- icucallback_t period_cb;
- /**
- * @brief Callback for timer overflow.
- */
- icucallback_t overflow_cb;
- /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief Structure representing an ICU driver.
- */
-struct ICUDriver {
- /**
- * @brief Driver state.
- */
- icustate_t state;
- /**
- * @brief Current configuration data.
- */
- const ICUConfig *config;
-#if defined(ICU_DRIVER_EXT_FIELDS)
- ICU_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Clock value for this unit.
- */
- uint32_t clock;
- /**
- * @brief eTimer submodule number.
- */
- uint32_t smod_number;
- /**
- * @brief Pointer to the eTimerx registers block.
- */
- volatile struct spc5_etimer *etimerp;
- /**
- * @brief CCR register used for width capture.
- */
- volatile vuint16_t *wccrp;
- /**
- * @brief CCR register used for period capture.
- */
- volatile vuint16_t *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- * edge and the stop edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- * edge and the next start edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_SMOD0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_SMOD1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_SMOD2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_SMOD3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_SMOD4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_SMOD5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_SMOD6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_SMOD7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_SMOD8 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_SMOD9 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#if SPC5_ICU_USE_SMOD10 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD11;
-#endif
-
-#if SPC5_ICU_USE_SMOD11 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD12;
-#endif
-
-#if SPC5_ICU_USE_SMOD12 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD13;
-#endif
-
-#if SPC5_ICU_USE_SMOD13 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD14;
-#endif
-
-#if SPC5_ICU_USE_SMOD14 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD15;
-#endif
-
-#if SPC5_ICU_USE_SMOD15 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD16;
-#endif
-
-#if SPC5_ICU_USE_SMOD16 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD17;
-#endif
-
-#if SPC5_ICU_USE_SMOD17 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD18;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void icu_lld_init(void);
- void icu_lld_start(ICUDriver *icup);
- void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h b/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h deleted file mode 100644 index 390af2ec8..000000000 --- a/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h +++ /dev/null @@ -1,316 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eTimer_v1/etimer.h
- * @brief SPC5xx eTimer header file.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ETIMER_H_
-#define _ETIMER_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief SPC5 FlexPWM registers block.
- * @note Redefined from the SPC5 headers because the non uniform
- * declaration of the SubModules registers among the various
- * sub-families.
- */
-struct spc5_etimer_submodule {
-
- union {
- vuint16_t R;
- struct {
- vuint16_t COMP1 :16;
- } B;
- } COMP1; /* Compare Register 1 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t COMP2 :16;
- } B;
- } COMP2; /* Compare Register 2 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPT1 :16;
- } B;
- } CAPT1; /* Capture Register 1 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CAPT2 :16;
- } B;
- } CAPT2; /* Capture Register 2 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t LOAD :16;
- } B;
- } LOAD; /* Load Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t HOLD :16;
- } B;
- } HOLD; /* Hold Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CNTR :16;
- } B;
- } CNTR; /* Counter Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CNTMODE :3;
- vuint16_t PRISRC :5;
- vuint16_t ONCE :1;
- vuint16_t LENGTH :1;
- vuint16_t DIR :1;
- vuint16_t SECSRC :5;
- } B;
- } CTRL; /* Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t OEN :1;
- vuint16_t RDNT :1;
- vuint16_t INPUT :1;
- vuint16_t VAL :1;
- vuint16_t FORCE :1;
- vuint16_t COFRC :1;
- vuint16_t COINIT :2;
- vuint16_t SIPS :1;
- vuint16_t PIPS :1;
- vuint16_t OPS :1;
- vuint16_t MSTR :1;
- vuint16_t OUTMODE :4;
- } B;
- } CTRL2; /* Control Register 2 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t STPEN :1;
- vuint16_t ROC :2;
- vuint16_t FMODE :1;
- vuint16_t FDIS :4;
- vuint16_t C2FCNT :3;
- vuint16_t C1FCNT :3;
- vuint16_t DBGEN :2;
- } B;
- } CTRL3; /* Control Register 3 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :6;
- vuint16_t WDF :1;
- vuint16_t RCF :1;
- vuint16_t ICF2 :1;
- vuint16_t ICF1 :1;
- vuint16_t IEHF :1;
- vuint16_t IELF :1;
- vuint16_t TOF :1;
- vuint16_t TCF2 :1;
- vuint16_t TCF1 :1;
- vuint16_t TCF :1;
- } B;
- } STS; /* Status Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t ICF2DE :1;
- vuint16_t ICF1DE :1;
- vuint16_t CMPLD2DE :1;
- vuint16_t CMPLD1DE :1;
- vuint16_t :2;
- vuint16_t WDFIE :1;
- vuint16_t RCFIE :1;
- vuint16_t ICF2IE :1;
- vuint16_t ICF1IE :1;
- vuint16_t IEHFIE :1;
- vuint16_t IELFIE :1;
- vuint16_t TOFIE :1;
- vuint16_t TCF2IE :1;
- vuint16_t TCF1IE :1;
- vuint16_t TCFIE :1;
- } B;
- } INTDMA; /* Interrupt and DMA Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CMPLD1 :16;
- } B;
- } CMPLD1; /* Compare Load Register 1 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CMPLD2 :16;
- } B;
- } CMPLD2; /* Compare Load Register 2 */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t CLC2 :3;
- vuint16_t CLC1 :3;
- vuint16_t CMPMODE :2;
- vuint16_t CPT2MODE :2;
- vuint16_t CPT1MODE :2;
- vuint16_t CFWM :2;
- vuint16_t ONESHOT :1;
- vuint16_t ARM :1;
- } B;
- } CCCTRL; /* Compare and Capture Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t FILTCNT :3;
- vuint16_t FILTPER :8;
- } B;
- } FILT; /* Input Filter Register */
-
-};
-/* end of ETIMER_CHANNEL_tag */
-
-struct spc5_etimer {
-
- struct spc5_etimer_submodule CHANNEL[8];
-
- union {
- vuint16_t R;
- struct {
- vuint16_t WDTOL :16;
- } B;
- } WDTOL; /* Watchdog Time-out Low Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t WDTOH :16;
- } B;
- } WDTOH; /* Watchdog Time-out High Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :3;
- vuint16_t FTEST :1;
- vuint16_t FIE :4;
- vuint16_t :4;
- vuint16_t FLVL :4;
- } B;
- } FCTRL; /* Fault Control Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :4;
- vuint16_t FFPIN :4;
- vuint16_t :4;
- vuint16_t FFLAG :4;
- } B;
- } FSTS; /* Fault Status Register */
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :5;
- vuint16_t FFILTCNT :3;
- vuint16_t FFILTPER :8;
- } B;
- } FFILT; /* Fault Filter Register */
-
- int16_t ETIMER_reserved1;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :8;
- vuint16_t ENBL :8;
- } B;
- } ENBL; /* Channel Enable Register */
-
- int16_t ETIMER_reserved2;
-
- union {
- vuint16_t R;
- struct {
- vuint16_t :11;
- vuint16_t DREQ :5;
- } B;
- } DREQ[4]; /* DMA Request 0->3 Select Register */
-
-};
-/* end of ETIMER_tag */
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name FlexPWM units references
- * @{
- */
-#if SPC5_HAS_ETIMER0
-#define SPC5_ETIMER_0 (*(volatile struct spc5_etimer *)0xFFE18000UL)
-#endif
-
-#if SPC5_HAS_ETIMER1
-#define SPC5_ETIMER_1 (*(volatile struct spc5_etimer *)0xFFE1C000UL)
-#endif
-
-#if SPC5_HAS_ETIMER2
-#define SPC5_ETIMER_2 (*(volatile struct spc5_etimer *)0xFFE20000UL)
-#endif
-/** @} */
-
-#endif /* _FLEXPWM_H_ */
-
-/** @} */
|