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* added tests for new verilog featuresClifford Wolf2014-06-072-6/+37
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* Added tests/simple/repwhile.vClifford Wolf2014-06-061-0/+20
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* Progress in Verific bindingsClifford Wolf2014-03-173-2/+13
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* Progress in Verific bindingsClifford Wolf2014-03-141-5/+9
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* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
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* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
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* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
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* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-217-0/+214
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* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-192-0/+170
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* Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
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* Updated ABC and some related changesClifford Wolf2014-02-131-2/+1
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* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-121-1/+2
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* Added test cases for expose -evert-dffClifford Wolf2014-02-082-0/+48
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* Added splice commandClifford Wolf2014-02-072-0/+28
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* Added counters sat test caseClifford Wolf2014-02-062-0/+45
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* Removed old unused files from tests/Clifford Wolf2014-02-0514-2602/+0
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* Added test cases for sat commandClifford Wolf2014-02-046-0/+126
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+39
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* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-031-50/+10
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* Bugfix in name resolution with generate blocksClifford Wolf2014-01-301-0/+24
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* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+17
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* Added autotest.sh -p optionClifford Wolf2014-01-021-3/+8
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* Use "abc -dff" in "make test"Clifford Wolf2013-12-311-3/+2
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* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-311-1/+1
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-271-0/+11
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* Added multiplier test case from eda playgroundClifford Wolf2013-12-181-0/+132
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* Added elsif preproc supportClifford Wolf2013-12-181-1/+229
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* Added support for macro argumentsClifford Wolf2013-12-181-0/+9
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* Various improvements in support for generate statementsClifford Wolf2013-12-041-0/+27
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-1/+1
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* Fix in sincos testbench genClifford Wolf2013-12-041-1/+1
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* Added sincos test caseClifford Wolf2013-12-041-0/+124
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-242-2/+2
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* Removed now obsolete test casesClifford Wolf2013-11-243-72/+0
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-241-1/+7
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* Added modelsim support to autotestClifford Wolf2013-11-242-2/+31
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* Another name resolution bugfix for generate blocksClifford Wolf2013-11-201-0/+48
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* Implemented indexed part selectsClifford Wolf2013-11-201-0/+5
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* Implemented part/bit select on memory readClifford Wolf2013-11-201-0/+41
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* Added additional mem2reg testcaseClifford Wolf2013-11-181-0/+28
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-181-0/+22
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* Fixed handling of power operatorClifford Wolf2013-11-071-0/+15
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* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵Clifford Wolf2013-11-021-6/+6
| | | | before constfold fixes)
* Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-021-0/+7
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-241-12/+26
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* Improved handling of dff with async resetsClifford Wolf2013-10-211-0/+39
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-153-5/+5
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* Added support for "2**n" shifter encodingClifford Wolf2013-08-121-24/+29
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* Added $div and $mod technology mappingClifford Wolf2013-08-092-24/+43
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* More fixes in ternary op sign handlingClifford Wolf2013-07-121-0/+8
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