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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:59:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:59:58 +0100 |
| commit | bada3ee815c05933723a64234106ab68b7599568 (patch) | |
| tree | a3a445eab7abd0e4cf3c6889acdeb33e9e8874a3 /tests | |
| parent | 4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c (diff) | |
| download | yosys-bada3ee815c05933723a64234106ab68b7599568.tar.gz yosys-bada3ee815c05933723a64234106ab68b7599568.tar.bz2 yosys-bada3ee815c05933723a64234106ab68b7599568.zip | |
Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 541da483e..e2c6303da 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -ev -yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v |