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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:14:38 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:14:38 +0100 |
| commit | 3c5e9730924e5cc1ac5769f1fadd3f1d15a2aaa3 (patch) | |
| tree | 9283e6a25f44605c994ca7c1ced72a493c17ca6b /tests | |
| parent | 81b3f52519d388f252405fa7cc7472ca9e51bc49 (diff) | |
| download | yosys-3c5e9730924e5cc1ac5769f1fadd3f1d15a2aaa3.tar.gz yosys-3c5e9730924e5cc1ac5769f1fadd3f1d15a2aaa3.tar.bz2 yosys-3c5e9730924e5cc1ac5769f1fadd3f1d15a2aaa3.zip | |
Use private namespace in mem_simple_4x1_map
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_map.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index d207cc1bc..5f93914c1 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -56,7 +56,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); genvar i; generate for (i = 0; i < WIDTH; i=i+1) begin:slice - mem_4x1_generator #( + \$__mem_4x1_generator #( .ABITS(ABITS), .SIZE(SIZE) ) bit_slice ( @@ -71,7 +71,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); endgenerate endmodule -module mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); +module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); parameter ABITS = 4; parameter SIZE = 16; @@ -85,7 +85,7 @@ module mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); if (ABITS > 4) begin wire high_rd_data, low_rd_data; if (SIZE > 2**(ABITS-1)) begin - mem_4x1_generator #( + \$__mem_4x1_generator #( .ABITS(ABITS-1), .SIZE(SIZE - 2**(ABITS-1)) ) part_high ( @@ -99,7 +99,7 @@ module mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); end else begin assign high_rd_data = 1'bx; end - mem_4x1_generator #( + \$__mem_4x1_generator #( .ABITS(ABITS-1), .SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE) ) part_low ( |