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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-18 13:21:02 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-18 13:21:02 +0100 |
| commit | 921064c20044f72a64bec12dbd73103bdd3f45e3 (patch) | |
| tree | b1b7e24b7756f45c66a617afc17496711afc0d33 /tests | |
| parent | 09bd82db217d27930d1eeec8d0dfd1e014c675b4 (diff) | |
| download | yosys-921064c20044f72a64bec12dbd73103bdd3f45e3.tar.gz yosys-921064c20044f72a64bec12dbd73103bdd3f45e3.tar.bz2 yosys-921064c20044f72a64bec12dbd73103bdd3f45e3.zip | |
Added support for macro arguments
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/macros.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/simple/macros.v b/tests/simple/macros.v new file mode 100644 index 000000000..e2025717f --- /dev/null +++ b/tests/simple/macros.v @@ -0,0 +1,9 @@ +module test(a, y); +`define MSB_LSB_SEP : +`define get_msb(off, len) ((off)+(len)-1) +`define get_lsb(off, len) (off) +`define sel_bits(offset, len) `get_msb(offset, len) `MSB_LSB_SEP `get_lsb(offset, len) +input [31:0] a; +output [7:0] y; +assign y = a[`sel_bits(16, 8)]; +endmodule |