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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 13:05:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 13:05:27 +0100 |
| commit | 92035fb38ef8e7ac6319af659f7d682a047d2f70 (patch) | |
| tree | addf8c0a087eac819af1d869af61608061fbfa34 /tests | |
| parent | c4c299eb5a3d9c2b7c9932efb35669c09c1aacb4 (diff) | |
| download | yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.tar.gz yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.tar.bz2 yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.zip | |
Implemented indexed part selects
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/partsel.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v new file mode 100644 index 000000000..acfc1ca5d --- /dev/null +++ b/tests/simple/partsel.v @@ -0,0 +1,5 @@ +module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down); +wire [5:0] offset = idx << 2; +assign slice_up = data[offset +: 4]; +assign slice_down = data[offset + 3 -: 4]; +endmodule |