| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 10 | -17/+21 |
| * | Make equivalence work with latest master | Miodrag Milanovic | 2019-10-17 | 3 | -8/+8 |
| * | remove not needed top module | Miodrag Milanovic | 2019-10-17 | 2 | -20/+2 |
| * | remove not needed top module | Miodrag Milanovic | 2019-10-17 | 2 | -17/+2 |
| * | split muxes synth per type | Miodrag Milanovic | 2019-10-17 | 2 | -39/+39 |
| * | Test dffs separetely | Miodrag Milanovic | 2019-10-17 | 2 | -26/+19 |
| * | Split latches into separete tests | Miodrag Milanovic | 2019-10-17 | 2 | -42/+27 |
| * | Fix formatting | Miodrag Milanovic | 2019-10-17 | 1 | -1/+8 |
| * | Clean verilog code from not used define block | Miodrag Milanovic | 2019-10-17 | 2 | -12/+0 |
| * | Removed alu and div_mod test as agreed, ignore generated files | Miodrag Milanovic | 2019-10-17 | 5 | -70/+1 |
| * | Test per flip-flop type | Miodrag Milanovic | 2019-10-17 | 2 | -47/+37 |
| * | Add -assert | Eddie Hung | 2019-10-17 | 1 | -1/+1 |
| * | Use built-in async2sync call as per #1417 | Eddie Hung | 2019-10-17 | 1 | -4/+0 |
| * | Update mul test to DSP48E1 | Eddie Hung | 2019-10-17 | 1 | -9/+2 |
| * | Update area for div_mod | Eddie Hung | 2019-10-17 | 1 | -6/+6 |
| * | Add comment for lack of tristate logic pointing to #1225 | Eddie Hung | 2019-10-17 | 1 | -1/+1 |
| * | Move $x to end as 7f0eec8 | Eddie Hung | 2019-10-17 | 1 | -1/+1 |
| * | adffs test update (equiv_opt -multiclock) | SergeyDegtyar | 2019-10-17 | 1 | -5/+6 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Fix div_mod test | Sergey | 2019-10-17 | 1 | -1/+1 |
| * | Add comment with expected behavior for latches,tribuf tests;Update adffs test | SergeyDegtyar | 2019-10-17 | 4 | -14/+11 |
| * | Fix latches.ys test | SergeyDegtyar | 2019-10-17 | 1 | -4/+3 |
| * | Add smoke tests to tests/xilinx | SergeyDegtyar | 2019-10-17 | 29 | -9/+654 |
| * | Use equiv_opt -async2sync for xilinx | Eddie Hung | 2019-10-03 | 1 | -3/+1 |
| * | Add latch test modified from #1363 | Eddie Hung | 2019-09-30 | 2 | -0/+73 |
| * | Add mac.sh and macc_tb.v for testing | Eddie Hung | 2019-09-19 | 2 | -0/+99 |
| * | Remove stat | Eddie Hung | 2019-09-18 | 1 | -1/+0 |
| * | Add .gitignore | Eddie Hung | 2019-09-18 | 1 | -0/+1 |
| * | Refine macc testcase | Eddie Hung | 2019-09-18 | 2 | -9/+17 |
| * | Add AREG=2 BREG=2 test | Eddie Hung | 2019-09-11 | 1 | -2/+6 |
| * | Update test with a/b reset | Eddie Hung | 2019-09-11 | 1 | -2/+4 |
| * | Extend test for RSTP and RSTM | Eddie Hung | 2019-09-11 | 2 | -3/+50 |
| * | Add SIMD test | Eddie Hung | 2019-09-09 | 1 | -0/+25 |
| * | Update macc test | Eddie Hung | 2019-09-06 | 2 | -42/+42 |
| * | Add macc test, with equiv_opt not currently passing | Eddie Hung | 2019-08-30 | 2 | -0/+54 |
| * | Update test for ffM | Eddie Hung | 2019-08-30 | 1 | -2/+2 |
| * | Add mul_unsigned test | Eddie Hung | 2019-08-30 | 2 | -0/+41 |
| * | Add .gitignore | Eddie Hung | 2019-08-28 | 1 | -0/+3 |
| * | Use test_pmgen for xilinx_srl | Eddie Hung | 2019-08-28 | 1 | -0/+57 |
| * | Do not simplemap for variable test | Eddie Hung | 2019-08-28 | 1 | -2/+2 |
| * | Add xilinx_srl test | Eddie Hung | 2019-08-28 | 3 | -0/+127 |
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index : iCE40/yosys | |
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