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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 10:13:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 10:13:13 -0700 |
| commit | 6a95ecd41d31a841537357a1ffaabf4ea5c7ed93 (patch) | |
| tree | a32d29690ce0ceb089d832269d4565a2765b3b14 /tests/xilinx | |
| parent | 36d6db7f8aac6568acc2fb2d4ea5a5427d00d667 (diff) | |
| download | yosys-6a95ecd41d31a841537357a1ffaabf4ea5c7ed93.tar.gz yosys-6a95ecd41d31a841537357a1ffaabf4ea5c7ed93.tar.bz2 yosys-6a95ecd41d31a841537357a1ffaabf4ea5c7ed93.zip | |
Update test with a/b reset
Diffstat (limited to 'tests/xilinx')
| -rw-r--r-- | tests/xilinx/macc.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index c6ad2a578..5dc99ab8e 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -61,10 +61,12 @@ always @(posedge clk) begin // Store accumulation result into a register adder_out <= adder_out + mult_reg; end - if (rst) begin + if (rst) begin + a_reg <= 0; + b_reg <= 0; mult_reg <= 0; adder_out <= 0; - end + end end // Output accumulation result |