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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 09:19:17 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:42 +0200 |
| commit | fba6229718a45188514e016eec8678f1facb82a4 (patch) | |
| tree | 590ed2c20421f0f21fcee520f8100bba2e5cddbe /tests/xilinx | |
| parent | 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 (diff) | |
| download | yosys-fba6229718a45188514e016eec8678f1facb82a4.tar.gz yosys-fba6229718a45188514e016eec8678f1facb82a4.tar.bz2 yosys-fba6229718a45188514e016eec8678f1facb82a4.zip | |
Fix formatting
Diffstat (limited to 'tests/xilinx')
| -rw-r--r-- | tests/xilinx/adffs.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 7edab67c7..2d23749ac 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE + select -assert-none t:BUFG t:FDCE %% t:* %D + design -load read proc hierarchy -top adffn @@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:LUT1 + select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D + design -load read proc hierarchy -top dffs @@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 + select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + design -load read proc hierarchy -top ndffnr @@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:LUT2 -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
\ No newline at end of file + +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D |