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* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
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| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
* | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-0/+13
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| * | tests: tidy up testcaseEddie Hung2020-06-031-3/+0
| * | tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
* | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
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| * | | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* | | allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
* tests: remove write_ilangEddie Hung2020-04-202-3/+0
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
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| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| * ice40: remove impossible test.whitequark2020-02-061-15/+0
* | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-012-7/+3
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| * | Simplify breaking tests/arch/*/fsm.ys testsEddie Hung2020-03-202-7/+3
* | | fix argument order for macOS compatibilityN. Engelhardt2020-03-181-3/+3
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* | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+2
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| * | Change attribute search value to specify precise location instead of simple l...Alberto Gonzalez2020-02-241-2/+2
* | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
* | | Cleanup testsEddie Hung2020-02-271-0/+18
* | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
* | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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* | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
* | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
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* Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-052-5/+5
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| * Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-057-28/+173
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| * | Update tests with reduced areaEddie Hung2020-01-212-6/+6
* | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-033-4/+61
* | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
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| * | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1