| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ABC9: Cell Port Bug Patch (#3670) | Benjamin Barzen | 2023-04-22 | 2 | -0/+16 |
| * | add additional dff and lutram tests | Miodrag Milanovic | 2023-04-06 | 2 | -0/+57 |
| * | add test for CCU2D | Miodrag Milanovic | 2023-04-06 | 1 | -0/+10 |
| * | Update tests | Miodrag Milanovic | 2023-03-20 | 7 | -16/+16 |
| * | fabulous: Add support for mapping carry chains | gatecat | 2023-02-27 | 1 | -0/+9 |
| * | Genericising bug1836.ys | KrystalDelusion | 2023-02-21 | 1 | -20/+12 |
| * | bug3205.ys removed | KrystalDelusion | 2023-02-21 | 1 | -57/+0 |
| * | Removing extra `default_nettype` lines | KrystalDelusion | 2023-02-21 | 1 | -2/+0 |
| * | Fix for sync_ram_sdp not being final module | KrystalDelusion | 2023-02-21 | 1 | -1/+1 |
| * | Tests for ram_style = "huge" | KrystalDelusion | 2023-02-21 | 4 | -0/+219 |
| * | Testing TDP synth mapping | KrystalDelusion | 2023-02-21 | 3 | -0/+49 |
| * | Asymmetric port ram tests with Xilinx | KrystalDelusion | 2023-02-21 | 3 | -0/+193 |
| * | Addings tests for #1836 and #3205 | KrystalDelusion | 2023-02-21 | 3 | -0/+120 |
| * | fabulous: Allow adding extra custom prims and map rules | gatecat | 2022-11-17 | 3 | -0/+21 |
| * | fabulous: improvements to the pass | gatecat | 2022-11-17 | 7 | -0/+141 |
| * | Reenable existing equiv_opt tests | Jannis Harder | 2022-10-07 | 2 | -3/+3 |
| * | Fix tests for check in equiv_opt | Jannis Harder | 2022-10-07 | 5 | -7/+17 |
| * | support file locations containing spaces | Miodrag Milanovic | 2022-08-08 | 1 | -0/+1 |
| * | gatemate: Add test for LUT tree mapping | gatecat | 2022-06-27 | 3 | -0/+813 |
| * | efinix: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -12/+1 |
| * | ice40: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -56/+0 |
| * | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 3 | -46/+15 |
| * | nexus: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -2/+2 |
| * | ecp5: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -135/+18 |
| * | intel_alm: M10K write-enable is negative-true | Lofty | 2022-03-09 | 1 | -1/+2 |
| * | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 1 | -3/+2 |
| * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 2 | -1/+14 |
| * | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 1 | -2/+2 |
| * | Add gitignore for gatemate | Miodrag Milanovic | 2021-12-03 | 1 | -0/+4 |
| * | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 1 | -4/+8 |
| * | synth_gatemate: Apply new test practice with assert-max | Patrick Urban | 2021-11-13 | 7 | -12/+12 |
| * | synth_gatemate: Fix fsm test | Patrick Urban | 2021-11-13 | 1 | -2/+2 |
| * | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 6 | -4/+20 |
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 14 | -0/+337 |
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 2 | -3/+3 |
| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 1 | -2/+3 |
| * | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -0/+7 |
| * | Gowin: deal with active-low tristate (#2971) | Pepijn de Vos | 2021-08-20 | 1 | -1/+2 |
| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 2 | -78/+156 |
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 2 | -25/+25 |
| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 1 | -0/+24 |
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 3 | -73/+73 |
| * | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 4 | -17/+14 |
| * | intel_alm: Fix illegal carry chains | gatecat | 2021-05-15 | 2 | -4/+4 |
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 13 | -41/+41 |
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 13 | -39/+39 |
| * | Add default assignments to SB_LUT4 | Claire Xenia Wolf | 2021-04-20 | 1 | -1/+1 |
| * | quicklogic: ABC9 synthesis | Lofty | 2021-04-17 | 6 | -17/+17 |
| * | quicklogic: Add .gitignore file for test outputs. | Marcelina Kościelnicka | 2021-03-23 | 1 | -0/+4 |
| * | quicklogic: PolarPro 3 support | Lofty | 2021-03-18 | 10 | -0/+262 |
