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author | Miodrag Milanović <mmicko@gmail.com> | 2020-01-29 11:18:06 +0100 |
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committer | GitHub <noreply@github.com> | 2020-01-29 11:18:06 +0100 |
commit | 71d148bcaa19c0339e214ba21ac9ec22f3cfbc6b (patch) | |
tree | f975e3d8f63fbc2ae5178ed7c2aa3f2ffeb600c0 /tests/arch | |
parent | d004953772bdf4b4183621c2cc2b776dbaa237af (diff) | |
parent | 94191a93ddf85f8849d40e5ee85fd659b0780994 (diff) | |
download | yosys-71d148bcaa19c0339e214ba21ac9ec22f3cfbc6b.tar.gz yosys-71d148bcaa19c0339e214ba21ac9ec22f3cfbc6b.tar.bz2 yosys-71d148bcaa19c0339e214ba21ac9ec22f3cfbc6b.zip |
Merge pull request #1559 from YosysHQ/efinix_test_fix
Fix for non-deterministic test
Diffstat (limited to 'tests/arch')
-rw-r--r-- | tests/arch/efinix/mux.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index b46f641e1..a5ab80d8b 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -36,6 +36,6 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:EFX_LUT4 +select -assert-max 12 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D |